Fast Hardware Implementations of Inversions in Small Finite Fields for Special Irreducible Polynomials on FPGAs

Haibo Yi,Weijian Li,Zhe Nie 보안공학연구지원센터 2016 International Journal of Security and Its Applicat Vol.10 No.9

Inversions in small finite fields are the most computationally intensive field arithmetic and have been playing a key role in areas of cryptography and engineering. The main algorithms for small finite field inversions are based on Fermat's little theorem, extended Euclidean algorithm, Itoh-Tsujii algorithm and other methods. In this brief, we present techniques to exploit special irreducible polynomials for fast inversions in small finite fields GF(2n) , where n is a positive integer and 0 < n < 16 . Then, we propose fast inversions based on Fermat's theorem for two special irreducible polynomials in small finite fields, i.e. trinomials and All-One-Polynomials (AOPs). Trinomials can be represented by polynomials xn + xm + 1 and AOPs can be represented by polynomials xn + Xn-1 + ... +1 , where m is a positive integer and 0 < m < n . Our designs have low hardware requirements, regular structures and are therefore suitable for hardware implementation. After that, our designs are programmed in Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) by using integrated environment Altera Quartus II and implemented on a low-cost Field- Programmable Gate Array (FPGA). The experimental results on FPGAs show that our designs provide significant reductions in executing time of inversions in small finite fields, e.g. the executing time of inversion in GF(27) is 18.80 ns and the executing time of inversion in GF(212) is 29.57 ns.

Fast Three-Input Multipliers over Small Composite Fields for Multivariate Public Key Cryptography

Haibo Yi,Weijian Li 보안공학연구지원센터 2015 International Journal of Security and Its Applicat Vol.9 No.9

Since quantum computer attacks will be threats to the current public key cryptographic systems, there has been a growing interest in Multivariate Public Key Cryptography (MPKC), which has the potential to resist such attacks. Finite field multiplication is playing a crucial role in the implementations of multivariate cryptography and most of them use two-input multipliers. However, there exist multiple multiplications of three elements in multivariate cryptography. This motivates our work of designing three-input multipliers, which extend the improvements on multiplication of three elements in three directions. First, since multivariate cryptography can be implemented over small composite fields, our multipliers are designed over such fields. Second, since it requires multiplications of two and three elements, our multipliers can execute both of them. Third, our multipliers adapt table look-up and polynomial basis, since they are faster over specific fields, respectively. We demonstrate the improvement of our design mathematically. We implement our design on a Field-Programmable Gate Array (FPGA), which shows that our design is faster than other two-input multipliers when computing multiplication of three elements, e.g. multiplier with field size 256 is 28.4% faster. Our multipliers can accelerate multivariate cryptography and mathematical applications, e.g. TTS is 14% faster.

Development of Field Programmable Gate Array-based Reactor Trip Functions Using Systems Engineering Approach

정재천,Ibrahim Ahmed 한국원자력학회 2016 Nuclear Engineering and Technology Vol.48 No.4

Design engineering process for field programmable gate array (FPGA)-based reactor tripfunctions are developed in this work. The process discussed in this work is based on thesystems engineering approach. The overall design process is effectively implemented bycombining with design and implementation processes. It transforms its overall developmentprocess from traditional V-model to Y-model. This approach gives the benefit ofconcurrent engineering of design work with software implementation. As a result, it reducesdevelopment time and effort. The design engineering process consisted of five activities,which are performed and discussed: needs/systems analysis; requirementanalysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that triggerreactor trip when the process input value exceeds the setpoint. To implement designsynthesis effectively, a model-based design technique is implied. The finite-state machinewith data path structural modeling technique together with very high speed integratedcircuit hardware description language and the Aldec Active-HDL tool are used to design,model, and verify the reactor bistable trip functions for nuclear power plants.

Variable Step Size Maximum Power Point Tracker Using a Single Variable for Stand-alone Battery Storage PV Systems

Ahmed, Emad M.,Shoyama, Masahito The Korean Institute of Power Electronics 2011 JOURNAL OF POWER ELECTRONICS Vol.11 No.2

The subject of variable step size maximum power point tracking (MPPT) algorithms has been addressed in the literature. However, most of the addressed algorithms tune the variable step size according to two variables: the photovoltaic (PV) array voltage ($V_{PV}$) and the PV array current ($I_{PV}$). Therefore, both the PV array current and voltage have to be measured. Recently, maximum power point trackers that arc based on a single variable ($I_{PV}$ or $V_{PV}$) have received a great deal of attention due to their simplicity and ease of implementation, when compared to other tracking techniques. In this paper, two methods have been proposed to design a variable step size MPPT algorithm using only a single current sensor for stand-alone battery storage PV systems. These methods utilize only the relationship between the PV array measured current and the converter duty cycle (D) to automatically adapt the step change in the duty cycle to reach the maximum power point (MPP) of the PV array. Detailed analyses and flowcharts of the proposed methods are included. Moreover, a comparison has been made between the proposed methods to investigate their performance in the transient and steady states. Finally, experimental results with field programmable gate arrays (FPGAs) are presented to verify the performance of the proposed methods.

Variable Step Size Maximum Power Point Tracker Using a Single Variable for Stand-alone Battery Storage PV Systems

Emad M. Ahmed,Masahito Shoyama 전력전자학회 2011 JOURNAL OF POWER ELECTRONICS Vol.11 No.2

The subject of variable step size maximum power point tracking (MPPT) algorithms has been addressed in the literature. However, most of the addressed algorithms tune the variable step size according to two variables: the photovoltaic (PV) array voltage (VPV) and the PV array current (IPV). Therefore, both the PV array current and voltage have to be measured. Recently, maximum power point trackers that are based on a single variable (IPV or VPV) have received a great deal of attention due to their simplicity and ease of implementation, when compared to other tracking techniques. In this paper, two methods have been proposed to design a variable step size MPPT algorithm using only a single current sensor for stand-alone battery storage PV systems. These methods utilize only the relationship between the PV array measured current and the converter duty cycle (D) to automatically adapt the step change in the duty cycle to reach the maximum power point (MPP) of the PV array. Detailed analyses and flowcharts of the proposed methods are included. Moreover, a comparison has been made between the proposed methods to investigate their performance in the transient and steady states. Finally, experimental results with field programmable gate arrays (FPGAs) are presented to verify the performance of the proposed methods.

FPGA 기반 임베디드 시스템의 사이버 보안 위협 동향 분석

정세연(Seyeon Jeong),조민기(Mingi Cho),황은비(Eunbi Hwang),권태경(Taekyoung Kwon) 한국해군과학기술학회 2020 Journal of the KNST Vol.3 No.2

Field programmable gate array (FPGA) is field-programmable and reconfigurable integrated circuits, aiming at both hardware and software advantages. Therefore, the FPGA has the advantages that the development time is short, errors can be corrected, and the initial development cost is low. FPGAs with these advantages are considered important in embedded system design, and are used in various fields such as military systems, weapon systems, and aerospace. FPGA based embedded systems are designed with hardware manufacturers, third-party IP (intellectual property) providers, and outsourcing companies. Since multiple parties cooperate in the development, there is a possibility that a malicious attacker in an arbitrary party could inject the hardware trojan. In this paper, we identified and analyzed security threats targeting FPGA-based embedded systems.

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials

Sudha Ellison Mathe,Lakshmi Boppana 한국전자통신연구원 2017 ETRI Journal Vol.39 No.4

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

Design and Implementation of an FPGA-based Real-time Simulator for a Dual Three-Phase Induction Motor Drive

Raul Gregor,Guido Valenzano,Jorge Rodas,Jose Rodriguez-Pineiro,Derlis Gregor 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.2

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

Design and Implementation of an FPGA-based Real-time Simulator for a Dual Three-Phase Induction Motor Drive

Gregor, Raul,Valenzano, Guido,Rodas, Jorge,Rodriguez-Pineiro, Jose,Gregor, Derlis The Korean Institute of Power Electronics 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.2

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

Critical analysis of random frequency inverted sine carrier PWM fortification for half-controlled bipolar three-phase inverters

Muthukumar, P.,Padmasuresh, L.,Eswaramoorthy, K.,Jeevananthan, S. The Korean Institute of Power Electronics 2020 JOURNAL OF POWER ELECTRONICS Vol.20 No.2

The inverted sine carrier-based pulse width modulation scheme has been acknowledged for fundamental fortification in DC-AC conversion. This paper suggests a randomized inverted sine carrier for the half-controlled PWM switching strategy of a three-phase voltage source inverter to enhance its ability to spread harmonic power. A detailed study of the proposed modulation technique is presented through MATLAB-Simulink, and switching pulses are generated in the ModelSim digital environment. Harmonic analyses and assessments of different performance measures such as power spectrum density, harmonic spread factor, total harmonic distortion and dominating harmonic orders for various modulation indices have been carried out. Simulation and experimental results show that the proposed PWM method can spread harmonic power in output voltage better than the conventional SPWM or SVPWM. For real-time digital implementation, the gating signals are generated using a field-programmable gate array Spartan XC3S500E-320F device.