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Design FPGA-Based Fuzzification Algorithm for Model-free Control Techniques
Farzin Piltan,Maryam Rahmani,Omid Mahmoudi,Meysam Esmaeili,Mohammad Ali Tayebi,Mahsa Piltan,Hamid Cheraghi 보안공학연구지원센터 2016 International Journal of Hybrid Information Techno Vol.9 No.8
Many of fuzzy control applications require real-time operation; higher density programmable logic devices such as field programmable gate array (FPGA) can be used to integrate large amounts of logic in a single IC. This work, proposes a developed method to fuzzifier algorithm with optimal-tunable gains method-using FPGA. The maximum frequency in FPGA-based design is about 72.4 MHz and the delay time in this design is about 13.78 ns. It is observed that this algorithm is able to make as a fast response at 13.78 clock period with 72.4 of a maximum frequency and 2.1 ns for minimum input arrival time after clock. From investigation and synthesis summary, 24.3 for maximum input arrival time after clock with 13.9 MHZ frequencies, this design has 13.78 ns delays for each controller to 46 logic elements and the offset before CLOCK is 82.1 ns.
Research on FPGA-Based Controller for Nonlinear System
Farzin Piltan,Maryam Rahmani,Meysam Esmaeili,Mohammad Ali Tayebi,Mahsa Piltan Hamid Cheraghi,Mohammad R. Rashidian,Arzhang Khajeh 보안공학연구지원센터 2015 International Journal of u- and e- Service, Scienc Vol.8 No.3
Many of linear control applications require real-time operation; higher density programmable logic devices such as field programmable gate array (FPGA) can be used to integrate large amounts of logic in a single IC. This work, proposes a developed method to design PD controller (PDC) with optimal- gains using FPGA. The method used to design PD controller is to design it as digital design Proportional and Derivative controller in parallel through the summer. The proposed design is 32-bits FPGA-based controller (32PDC), which uses 32-bits for each input/output variable. The single joint of robot is used to test the controller in simulation environments, using VHDL code for the purpose of simulation in Xilinx. The same design is coded in MATLAB environment (MPDC) in order to make a comparison with the proposed FPGA-based design. PDC needs 16 clock cycles to complete one action with maximum frequency of 108.5 MHz. 32PDC is able to produce an output in 13.24 MHz with the robot system. Therefore, the proposed controller will be able to control a wide range of the systems with high sampling rate and 75.545 ns delays.