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Kenji OHNO,Hiroki MATSUMOTO,Kenji MURAO 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
As the chip integration advances toward the CMOS VLSI integrated systems, on-chip Digital-to-Analog Converter (DAC) becomes more important building blocks. Key technologies in DAC is fabrication at low-cost and operation on high-performance. Highresolution and Low-Voltage DAC is required in many fields. Their advantage extends to mixed-signal systems where both frequency higher, the device shrinks into deep sub-micrometer. However the shrinking device dimensions also imply proportional scalling of power supply voltage. Advantages of alogorithmic DAC using Switched-Capacitor (SC) are suitable to the above requirement. SC operates on small chip area, low consumption of electoric power, and is compatible to MOS IC. To operate under low supply voltage, terminal of NMOS analog switch should connect to ground or virtual ground.[1] However, major performance of conventional algolithmic DAC is limited by offset voltage and spike.[2] In this paper, they shows two Low-Voltage SC cyclic DACs. They are proposed which consists of a switch, capacitor, MOSFET and operational amplifier (op-amp). Circuit operation is evaluated on SIMetrix.
Spike-compensated Low-Voltage Unity-Gain-Reset Switched-Capacitor Cyclic Digital-to-Analog Converter
Kenji OHNO,HirokiMATSUMOTO,Kenji MURAO 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
As the chip integration advances toward the CMOS VLSI integrated systems, on-chip Digital-to-Analog Converter (DAC) becomes more important building blocks. Key technologies in DAC is fabrication at low-cost and operation on high-performance. Highresolution and Low-Voltage DAC is required in many fields. Their advantage extends to mixed-signal systems where both frequency higher, the device shrinks into deep sub-micrometer. However the shrinking device dimensions also imply proportional scalling of power supply voltage. Advantages of Alogorithmic DAC using Switched-Capacitor (SC) are suitable to the above requirement. SC are small chip area, low consumption of electoric power, and compatibility to MOS IC. To operate under low supply voltage, terminal of NMOS analog switch should connect to ground or virtual ground. However, major performance of conventional algolithmic DAC is limited by offset voltage and spike. In this paper, it shows a Low-Voltage SC cyclic DAC. It is proposed which consists of a switch, capacitor, MOSFET and op-amp. Circuit operation is evaluated on SIMetrix.
( Kenji S. Murao ),( Taylor K. Bloedon ),( Rock Braithwaite ),( Young Sub Kwon ) 한국체육학회 2018 International journal of human movement science Vol.12 No.1
The purpose of this study was to develop a sports-specific anaerobic capacity test for soccer players that could be administered on commercial treadmills found in most exercise facilities. The Anaerobic Speed Test (AST) is an anaerobic capacity test on a treadmill, however the testing protocol (20% incline, 214 meter/min) cannot be completed on commercial treadmills because they have a maximum incline setting of 15%. This study newly developed the modified Anaerobic Speed Test (mAST) protocol (15% incline, 244 meter/min) through the use of an ACSM metabolic equation to predict energy expenditure equivalent to that of the AST. Fifteen NCAA Division II male soccer players (mean ± SD, age = 20 ± 1.9 yr; height = 181.3 ± 7.9 cm; weight = 74.8 ± 5.2 kg) participated in this study. Subjects participated in three testing days, one AST trial and two mAST trials all done on separate days, and total run time in seconds was recorded for each trial. Mean AST run times (60.5 ± 10.6) had a significantly positive correlation (p<0.001) with mean trial 1 mAST run times (71.9 ± 9.5). Mean trial 1 mAST run times (71.9 ± 9.5) had a significantly strong, positive correlation (p<0.001) with mean trial 2 mAST run times (75.7±10.2). These findings suggest that the mAST is a valid and reliable measure of anaerobic capacity that is sports-specific to running-type athletes and can be administered on commercial treadmills.
Low-Power CMOS CNN Cell and its Application to an Oscillatory CNN
Hisashi Tanaka,Koichi Tanno,Hiroki Tamura,Kenji Murao 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, we propose a low-power operational transconductance amplifier (OTA) for low-power CMOS cellular neural networks (CNN) cell. The OTA use MOSFETs operating in the weak inversion region. The transconductance gm can be changed by changing the external bias voltage. The proposed OTA is verified by HSPICE simulations with the 0.18 ㎛ standard CMOS device parameters. From the results, the power consumption is less than 3.5 ㎼ with 1.2 V power supply. As an application of the proposed OTA, an oscillatory CNN circuit using two CNN cells with the proposed OTA is presented.