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Improving the Linearity of CMOS LNA Using the Post IM3 Compensator
Jingook Kim,Changjoon Park,Huijung Kim,Bumman Kim,Youngsik Kim 한국전자파학회JEES 2007 Journal of Electromagnetic Engineering and Science Vol.7 No.2
In this paper, a new linearization method has been proposed for a CMOS low noise amplifier(LNA) using the Post IM3 Compensator. The fundamental operating theory of the proposed method is to cancel the IM3 components of the LNA output signal by generating another IM3 components, which are out-phase with respect to that of the LNA, from the Post IM3 Compensator. A single stage common-source LNA has been designed to verify the linearity improvement of the proposed method through 0.13 ㎛ RF CMOS process for WiBro system. The designed LNA achieves +7.8 ㏈m of input-referred 3<SUP>rd</SUP>-order intercept point (ⅡP3) with 13.2 ㏈ of Power Gain, 1.3 ㏈ of noise figure and 5.7 mA @1.5 V power consumption. IIP3 is compared with a conventional single stage common-source LNA, and it shows IIP3 is increased by +12.5 ㏈ without degrading other features such as gain and noise figure.
Equivalent Circuit Model for Power Bus Design in Multi-Layer PCBs With Via Arrays
Jingook Kim,Shringarpure, K,Jun Fan,Joungho Kim,Drewniak, J L IEEE 2011 IEEE microwave and wireless components letters Vol.21 No.2
<P>An equivalent circuit model for multilayer power planes with multiple via arrays is proposed. The complexity of the actual geometry is greatly reduced in the circuit model with the accuracy maintained. The model is corroborated by measurements.</P>
Jingook Kim,Takita, Yuzo,Araki, Kenji,Jun Fan IEEE 2013 IEEE transactions on components, packaging, and ma Vol.3 No.9
<P>The concept of target impedance can be significantly improved, based on the rigorous closed-form expressions for transient supply voltage ripple excited by an integrated circuit (IC) switching current, for the power distribution network (PDN) with power traces that is commonly used in handheld devices. A systematic procedure for developing the target impedance is formulated, which is then applied to the PDN design of a handheld product. From measurements of transient IC switching currents, PDN impedance, and supply voltage ripple, it is shown that the proposed target impedance successfully correlates the PDN impedance in the frequency domain with the transient supply voltage ripple in the time domain.</P>
Kim, Jingook,Rotaru, M.D.,Baek, Seungyong,Park, Jongbae,Iyer, M.K.,Kim, Joungho IEEE 2006 IEEE transactions on electromagnetic compatibility Vol.48 No.2
As layout density increases in highly integrated multilayer printed circuit boards (PCBs), the noise that exists in the power distribution network (PDN) is increasingly coupled to the signal traces, and precise modeling to describe the coupling phenomenon becomes necessary. This paper presents a model to describe noise coupling between the power/ground planes and signal traces in multilayer systems. An analytical model for the coupling has been successfully derived, and the coupling mechanism was rigorously analyzed and clarified. Wave equations for a signal trace with power/ground noise were solved by imposing boundary conditions. Measurements in both the frequency and time domains have been conducted to confirm the validity of the proposed model.
Kim, Jingook,Lee, Heeseok,Kim, Joungho IEEE 2005 IEEE TRANSACTIONS ON ADVANCED PACKAGING Vol.28 No.4
Power/ground partitioning has been used to supply multivoltage levels and to isolate power/ground noise in high-speed multilayer printed circuit boards. However, the partitioning of the power/ground plane breaks the current return path of the signal current through either the power plane or the ground plane, which causes undesired effects such as signal distortion, crosstalk, and radiation. To control and suppress these undesired effects, we should understand the electromagnetic mechanism associated with them. In this paper, the mechanism of the reflection and the transmission of the signal by the slotted power/ground plane is well understood through an analysis of measurements based on time-domain reflectometry. Considering the propagation of a slot wave through the slot line on the power/ground plane, we have successfully explained the changes of the transmitted and reflected waveforms. Furthermore, we have numerically and experimentally investigated the effects of the power/ground partitioning on the radiated emission in various structures. Finally, it is confirmed that the employment of a stitching capacitor on the power/ground slot suppresses the signal distortion and the radiated emission significantly. When the size and the location of the stitching capacitor are designed, there should be a compromise between the noise isolation and the guarantee of the return current path, with considering the resonance frequencies of planes by the capacitor.
Jingook Kim,Jun Fan,Ruehli, A. E.,Joungho Kim,Drewniak, J. L. IEEE 2011 IEEE transactions on microwave theory and techniqu Vol.59 No.8
<P>Partial inductances are computed herein for the via transitions between parallel planes. A hybrid method proposed for the inductance calculation correlates the definition of the partial inductance and a resonant cavity model. The hybrid method is corroborated by comparison with the partial-element equivalent-circuit and the cavity methods, as well as measurements. The portions of the plane net and via net inductances are quantified, and the contribution of each plane current to the plane net inductance is quantitatively analyzed.</P>
Jingook Kim,Junho Lee,Sunki Cho,Chulsoon Hwang,Changwook Yoon,Jun Fan IEEE 2014 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.61 No.7
<P>An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-supply voltage fluctuations is proposed. To validate the theory, a silicon IC with noise-aggressing buffers and a victim buffer was designed, fabricated, and assembled in a printed circuit board (PCB). The overall power distribution network (PDN) of the IC and PCB was modeled from impedance measurements. The PDFs of the step pulse response of the victim buffer with power-supply voltage fluctuations were calculated and validated by comparisons with HSPICE and experimental results. The obtained PDFs due to power-supply voltage fluctuations could be combined with the statistical link simulation methods for quick estimation of bit error rate (BER).</P>
Design and Analysis of a Resonant Reactive Shield for a Wireless Power Electric Vehicle
Seonghwan Kim,Hyun-Ho Park,Jonghoon Kim,Jingook Kim,Seungyoung Ahn Professional Technical Group on Microwace Theory a 2014 IEEE Transactions on Microwave Theory and Techniqu Vol. No.
<P>In this paper, we propose the concept and design methodology for a resonant reactive shield for the reduction of magnetic field leakage from a wireless power transfer (WPT) systems. By using LC resonance, the reactive shield can generate a cancelling magnetic field to reduce the incident magnetic field from WPT coils and effectively reduce the total magnetic field without consuming additional power. The shielding effectiveness of the resonant reactive shield and its effect on WPT efficiency are analyzed with simulation and measurements. For practical application to wirelessly charged electric vehicles, an automatic tuning system for the resonant reactive shield is also proposed and implemented. The effectiveness of a resonant reactive shielding is verified by experiments in a wirelessly charged electric bus.</P>
Eunkyeong Park,Hyungsoo Kim,Jongjoo Shim,Yong-Ju Kim,Yun-Saing Kim,Jingook Kim [Institute of Electrical and Electronics Engineers 2015 IEEE transactions on electromagnetic compatibility Vol.57 No.4
<P>The jitter probability density function (PDF) at multistage output buffers due to supply voltage fluctuations is analytically derived. For experimental validation, an integrated circuit (IC) is designed, fabricated, and assembled in a printed circuit board (PCB). The on-chip supply voltage fluctuations are extracted from the simultaneous measurements at the pads on IC and PCB and used to calculate the jitter PDF of the multistage buffers. Also, characteristics of the output channels are measured and modeled with the separately designed channel pattern. Finally, the jitter PDFs for multistage buffers are calculated and compared with the measured jitter histograms.</P>
Common Mode Noise Reduction for an LLC Resonant Converter by Using Passive Noise Cancellation
Younggon Ryu,Sungnam Kim,Geunseok Jeong,Jaesu Park,Duil Kim,Jongwook Park,Jingook Kim,Ki Jin Han 한국전자파학회JEES 2015 Journal of Electromagnetic Engineering and Science Vol.15 No.2
This paper describes the application of a passive noise cancellation method to a prototype inductor-inductor-capacitor (LLC) resonant converter by placing a compensation winding in a transformer to reduce common mode noise. The connection method for the compensation winding is investigated. A circuit analysis is implemented for the displacement currents between the primary and secondary windings in the transformer. The analyzed displacement currents are verified by performing a circuit simulation and a proper compensation winding connection that reduces common mode noise is found. The measurement results show that common mode noise is reduced effectively up to 20 dB in the 1 to 7 MHz frequency region for the prototype LLC resonant converter by using the proposed passive noise cancellation method.