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Ultra-low power 1T-DRAM in FDSOI technology
El Dirani, H.,Lee, K.H.,Parihar, M.S.,Lacord, J.,Martinie, S.,Barbe, J-Ch.,Mescot, X.,Fonteneau, P.,Broquin, J.-E.,Ghibaudo, G.,Galy, Ph.,Gamiz, F.,Taur, Y.,Kim, Y.-T.,Cristoloveanu, S.,Bawedin, M. ELSEVIER 2017 MICROELECTRONIC ENGINEERING Vol.178 No.-
<P><B>Abstract</B></P> <P>A systematic study of a capacitorless 1T-DRAM fabricated in 28nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z<SUP>2</SUP>-FET memory cell features a large current sense margin and small OFF-state current at 25°C and 85°C. Moreover, low power consumption during state ‘1’ writing is achieved with ~0.5V programming voltage. These specifications make the Z<SUP>2</SUP>-FET an outstanding candidate for low-power eDRAM applications.</P> <P><B>Graphical abstract</B></P> <P>[DISPLAY OMISSION]</P>
Extended Analysis of the <tex> $Z^{2}$</tex> -FET: Operation as Capacitorless eDRAM
Navarro, Carlos,Lacord, Joris,Parihar, Mukta Singh,Adamu-Lema, Fikru,Duan, Meng,Rodriguez, Noel,Cheng, Binjie,El Dirani, Hassan,Barbe, Jean-Charles,Fonteneau, Pascal,Bawedin, Maryline,Millar, Campbell Institute of Electrical and Electronics Engineers 2017 IEEE transactions on electron devices Vol.64 No.11
<P>The Z(2)-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z(2)-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.</P>
<tex> ${Z}^{\textsf {2}}$</tex> -FET as Capacitor-Less eDRAM Cell For High-Density Integration
Navarro, Carlos,Duan, Meng,Parihar, Mukta Singh,Adamu-Lema, Fikru,Coseman, Stefan,Lacord, Joris,Lee, Kyunghwa,Sampedro, Carlos,Cheng, Binjie,El Dirani, Hassan,Barbe, Jean-Charles,Fonteneau, Pascal,Kim Institute of Electrical and Electronics Engineers 2017 IEEE transactions on electron devices Vol.64 No.12
<P>2-D numerical simulations are used to demonstrate the <TEX>${Z}^{\textsf {2}}$</TEX>-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.</P>