NEW SOI MATERIALS AND ADVANCED SOI DEVICES

SORIN CRISTOLOVEANU 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.45 No.2

Recent data on state-of-the-art SOI structures are reported, in order to reveal the key role of the device dimensions: thickness of the buried oxide, gate oxide, and silicon lm. MOSFET miniaturization enables new physics mechanisms. The self-heating problems in SOI MOSFETs can be solved by replacing the buried oxide with a dierent dielectric that oers improved thermal conductivity. The Gate-Induced Floating Body Eects (GIFBE) are described and shown to depend on the device geometry and frequency. In ultra-thin SOI lms, the coupling eects are amplied, leading to interesting consequences for double-gate operation. The operation principles and main features of transistors with 2, 3 or 4 gates are discussed.

Trends in SOI Technology: Hot and Green

Korean Physical Society 2011 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.58 No.5

Performance Improvement and Sub-60 mV/Decade Swing in AlGaN/GaN FinFETs by Simultaneous Activation of 2DEG and Sidewall MOS Channels

Xu, Yue,Cristoloveanu, Sorin,Bawedin, Maryline,Im, Ki-Sik,Lee, Jung-Hee Institute of Electrical and Electronics Engineers 2018 IEEE transactions on electron devices Vol. No.

<P>This paper presents a new concept, supported by 3-D TCAD simulations, for improving the performance and subthreshold swing (SS) of enhancement-mode AlGaN/GaN fin-shaped field-effect transistors (FinFETs). By choosing appropriate device parameters, the formation of 2-D electron gas (2DEG) can be delayed such as to ensure simultaneous activation of 2DEG and sidewall MOS channels at positive threshold voltage for normally off operation. The 2DEG channel starts forming in the middle of the fin, whereas the edges are depleted by the lateral MOS gates. Not only increasing the gate voltage does the 2DEG charge increase, but also the effective width is enlarged being less depleted by the gates. This double-2DEG mechanism adds to the regular MOS channels on the sidewalls and enables enhanced performance. The 3-D TCAD simulations indicate that narrow FinFET (20 nm) can exhibit excellent switching characteristics: very low SS of 55 mV/decade, below the 60 mV/decade limit, high on/off current ratio of 10<SUP>10</SUP>, and good current driving capability due to the added 2DEG channel contribution. The maximum transconductance is 350 mS/mm, the drain current reaches 380 mA/mm, and the on resistance is as low as 0.018 <TEX>$\text{m}\Omega \cdot \text {cm}^{2}$</TEX>.</P>

Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs

Yun, J.-G.,Cristoloveanu, S.,Bawedin, M.,Flandre, D.,Lee, Hi-Deok IEEE 2006 IEEE electron device letters Vol.27 No.2

A new type of abnormal drain current (ADC) effect in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs is reported. It is found that the drain current becomes abnormally large for specific front- and back-gate voltages. The drain current exhibits a transient effect due to the floating body behavior and no longer follows the conventional interface coupling theory for these specific front- and back-gate bias conditions. It is shown that the ADC can be generated by the combination of gate-induced drain leakage, transient effects, and parasitic bipolar transistor action in FD SOI MOSFETs.

Impact of Gate Misalignment in Triple-Gate MOSFETs Fabricated on SOI Substrate

Na, K.-I.,Cristoloveanu, S.,Xiong, W.,Lee, J.-H.,Bae, Y. The Electrochemical Society 2012 ECS solid state letters Vol.1 No.2

<P>The fin width non-uniformity in a dumbbell layout, caused by lithography, is a potential shortcoming of FinFETs, triple-gate, and nanowire FETs. We have investigated the electrical properties of especially designed n-channel triple-gate SOI MOSFETs, where the gate was intentionally misaligned. Misalignment degrades the device properties (threshold voltage, subthreshold slope, transconductance, DIBL) when the gate is shifted from the central region of the channel. The channel-to-substrate coupling is minimized in symmetrical devices where the gate controls the thinnest section of the fin. The misalignment effects are explained by accounting for fin width non-uniformity, short-channel, and 3D inter-gate coupling mechanisms. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.009202ssl] All rights reserved.</P>

Bufferless GaN-Based MOSFETs Fabricated on GaN-on-Insulator Wafer

Won, Chul-Ho,Caulmilone, Raphaë,l,Cristoloveanu, Sorin,Im, Ki-Sik,Lee, Jung-Hee Wiley (John WileySons) 2018 Physica status solidi. PSS. A, Applications and ma Vol.215 No.9

Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX

Ohata, A.,Bae, Y.,Fenouillet-Beranger, C.,Cristoloveanu, S. IEEE 2012 IEEE electron device letters Vol.33 No.3

<P>Carrier mobility <TEX>$(\mu)$</TEX> at various back-gate biases is studied for n- and p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that <TEX>$\mu$</TEX> did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest <TEX>$\mu$ </TEX> enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could conceal the superior <TEX>$\mu$</TEX> at the <TEX>$\hbox{Si/SiO}_{2}$</TEX> interface, <TEX>$\mu$</TEX> was maximized when both the front channel and BC were conducting. By contrast, <TEX>$\mu$ </TEX> in n-channel devices was maximized only when the BC was activated. This large <TEX>$\mu$</TEX> gain in p-channel devices is promising for further CMOS scaling.</P>

Heterojunction-Free GaN Nanochannel FinFETs With High Performance

Ki-Sik Im,Young-Woo Jo,Jae-Hoon Lee,Cristoloveanu, S.,Jung-Hee Lee IEEE 2013 IEEE electron device letters Vol.34 No.3

<P>Heavily doped GaN nanochannel fin-shaped field-effect transistors (FinFETs) without heterojunction have been fabricated and characterized for the first time. Simplified pragmatical technology for GaN epitaxial growth and FinFET process was used to achieve nanodevices with a channel width from 40 to 100 nm and a gate length of 1 μm. They exhibit excellent on-state performance, such as maximum drain current of 670 mA/mm and maximum transconductance of 168 mS/mm. Record off-state performance was measured: extremely low leakage current of ~ 10<SUP>-11</SUP> mA and source-drain breakdown voltage of ~280 V. The subthreshold slope of 68 mV/decade is close to the theoretical limit (60 mV/decade, so far achieved only in SOI MOSFETs) and leads to very high <I>I</I><SUB>on</SUB>/<I>I</I><SUB>off</SUB> ratio of 10<SUP>8</SUP> - 10<SUP>9</SUP>. The proposed heterojunction-free nanochannel GaN FinFET is a very promising candidate not only for high-performance and high-speed integrated circuits but also for high-power applications.</P>

Comparison for 1/ <tex> ${f}$</tex> Noise Characteristics of AlGaN/GaN FinFET and Planar MISHFET

Vodapally, Sindhuri,Theodorou, Christoforos G.,Bae, Youngho,Ghibaudo, Gerard,Cristoloveanu, Sorin,Im, Ki-Sik,Lee, Jung-Hee IEEE 2017 IEEE transactions on electron devices Vol.64 No.9

<P>DC and 1/f noise performances of the AlGaN/GaN fin-shaped field-effect transistor (FinFET) with fin width of 50 nm were analyzed. The FinFET exhibited approximately six times larger normalized drain current and transconductance, compared to those of the AlGaN/GaN planar metal-insulator-semiconductor heterostructure field-effect-transistor (MISHFET) fabricated on the same wafer. It was also observed that the FinFET exhibited improved noise performance with lower noise magnitude of 8.5x10(-15) A(2)/Hz when compared to the value of 8.7x10(-14)A(2)/Hz for the planar MISHFET. An intensive analysis indicated that both devices follow the carrier number fluctuation model, but the FinFET suffers much less charge trapping effect compared to the MISHFET (two orders lower charge trapping was observed). Moreover, the FinFET did not exhibit the Lorentz-like components, which explains that the depleted fin structure effectively prevents the carriers from being trapped into the underlying thick GaN buffer layer. On the other hand, the slope of the noise is 2 irrespective of drain voltage and apparently showed the Lorentz-like components, especially at high drain voltage in MISHFET device. This explains that the carrier trapping/detrapping between the 2-D electron gas channel and the GaN buffer layer is significant in MISHFET.</P>

Capacitance-voltage characterization of Al₂O₃/GaN-on-insulator (GaNOI) structures with TMAH surface treatment

Im, Ki-Sik,Kim, Jeong-Gil,Vodapally, Sindhuri,Caulmilone, Raphaë,l,Cristoloveanu, Sorin,Lee, Jung-Hee ELSEVIER 2017 MICROELECTRONIC ENGINEERING Vol.178 No.-

<P><B>Abstract</B></P> <P>The capacitance-voltage (<I>C-V</I>) characterizations of Al<SUB>2</SUB>O<SUB>3</SUB>/GaN-on-insulator (GaNOI) structure, prepared with the Smart Cut™ technology, with and without tetramethylammonium hydroxide (TMAH) surface treatment have been investigated. The GaNOI structure consists of a 150nm-thick GaN layer and a 800μm-thick Si<SUB>3</SUB>N<SUB>4</SUB>/SiO<SUB>2</SUB> buried insulating layer deposited on sapphire substrate. For fabrication of the MIS capacitor, an Al<SUB>2</SUB>O<SUB>3</SUB> layer with thickness of 28nm as a gate dielectric was deposited on the GaNOI wafer by atomic layer deposition (ALD). The calculated carrier concentration of the GaN layer on the buried insulator was increased to 2.8×10<SUP>17</SUP> cm<SUP>−3</SUP> from the value of ~5×10<SUP>16</SUP> cm<SUP>−3</SUP> for the as-grown undoped GaN layer prior to the wafer transfer. The MIS capacitor with TMAH surface treatment showed a positive threshold voltage shift with negligible hysteresis and low interface trap density compared to the capacitor without TMAH surface treatment. Severe frequency dispersion was observed regardless of the TMAH treatment due to the crystal defects generated during the complicated wafer transfer process.</P> <P><B>Highlights</B></P> <P> <UL> <LI> The Al<SUB>2</SUB>O<SUB>3</SUB>/GaN-on-insulator (GaNOI) capacitors were fabricated using TMAH surface treatment. </LI> <LI> The calculated doping density of GaN layer was obtained to 2.8×10<SUP>17</SUP> cm<SUP>−3</SUP>. </LI> <LI> This capacitors exhibited the severe frequency dispersion due to the crystal damaged GaN layer. </LI> <LI> The TMAH surface-treated MIS capacitor showed better performances compared to the TMAH-free device. </LI> </UL> </P> <P><B>Graphical abstract</B></P> <P>[DISPLAY OMISSION]</P>