이중 NAND 플래시 구조의 버퍼시스템에서 효율적 버퍼 크기

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2011 대한임베디드공학회논문지 Vol.6 No.6

As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

고성능 저전력 하이브리드 L2 캐시 메모리를 위한 연관사상 집합 관리

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2018 대한임베디드공학회논문지 Vol.13 No.3

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

범죄피해자 프로파일링 연구

정보성(BoSung Jung),김정규(JungGyu Kim) 마인드교육융합학회 2023 마인드 교육 Vol.2 No.1

이 연구는 서울에 위치한 전통시장인 인현시장의 상인을 대상으로 귀납적 프로파일링기법을 적용하여 범죄피해자를 중심으로 피해자 프로파일링 분석을 진행하였다. 연구순서는 우선 인현시장 내 상인 중 피해자의 인구사회학적 특징을 분석하였다. 분석을 위한 평가지표는 범죄유형과 인구사회학적 특징을 선정하였다. 분석결과, 피해자 대다수가 고연령자였으며 모든 범죄유형의 피해자 중 대다수가 기혼자로 밝혀졌다. 또한 절대다수의 범죄피해자는 상점의 사장이거나 사장의 가족으로 나타나, 이들을 대상으로 범죄예방교육 등 범죄를 예방할 수 있는 실질적인 정책개발의 필요성이 도출되었다. 소득수준은 도난피해자의 경우에 한해서 소득수준과 도난피해 간에 부적인 상관관계가 발견됐다. 즉 소득수준이 낮은 사람들이 도난의 피해를 더 많이 경험한 것으로 나타났다. 따라서 소득수준이 낮은 상인들을 대상으로 도난범죄 피해근절을 위한 다양한 정책이 검토될 필요성이 나타났다. 과거 범죄피해자는 형사사법 체제에서 비중이 극히 낮았다. 피해자 조사는 첫 번째로 그리고 무엇보다도 정황, 연관성 그리고 수사방향을 제공하는 수사도구이다. 특히 미제사건에 준하는 사건에서 철저한 피해자분석과 조사는 용의자를 한정하는데 중요한 역할을 하였다. 따라서 피해자를 형사사건 수사절차에서 중요한 대상으로 설정하고 이에 대한 깊이 있는 관찰과 연구가 세심하게 이루어져 할 것이다. The study applied inductive profiling techniques to merchants of Inhyeon Market, a representative traditional market in Jung-gu, the heart of Seoul, and conducted a victim profiling analysis focusing on crime victims among Inhyeon Market merchants. Specifically, the demographic and sociological characteristics of the victims among merchants in Inhyeon Market were analyzed. Evaluation indicators for analysis were selected by dividing them into crime types and demographic sociological characteristics. Analysis revealed that the majority of victims were elderly and the majority of victims of all crime types were married. In addition, as the majority of crime victims are found to be the president of the store or the family of the president, it is thought that practical policies should be prepared to prevent crime, such as crime prevention education, for them. In terms of income level, an inappropriate correlation between income level and theft damage was found only for victims of theft. In other words, it was confirmed that people with low income levels experienced more theft damage. Therefore, various policies should be prepared to eradicate theft crime damage for merchants with low income levels. In the past, crime victims were forgotten in the criminal justice system. Victim investigation is the first and most important investigative tool that provides context, relevance, and direction of investigation. In unsolved cases where the culprit is unknown, a thorough victim analysislimits the group of suspects. In order to find out who approached the victim, what, when, how, and where, the victim’s daily lifestyle and special activities should be investigated in detail. If we can understand how and why the criminal chose the victim, we will be able to identify the link between the victim and the criminal.

지역성을 이용한 하이브리드 메모리 페이지 교체 정책

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2017 대한임베디드공학회논문지 Vol.12 No.3

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

저전력 NAND 플래시 메모리를 위한 필터 버퍼의 효율성 분석

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2012 대한임베디드공학회논문지 Vol.7 No.4

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.

DRAM&PCM 하이브리드 메모리 시스템을 위한 능동적 페이지 교체 정책

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2018 대한임베디드공학회논문지 Vol.13 No.5

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

고성능 PCM&DRAM 하이브리드 메모리 시스템

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2016 대한임베디드공학회논문지 Vol.11 No.2

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

내장형 시스템을 위한 선택적 뱅크 알고리즘을 이용한 데이터 캐쉬 시스템

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 한국정보처리학회 2009 정보처리학회논문지 A Vol.16 No.2

캐쉬의 성능을 향상시키는 가장 효과적인 방법은 프로그램 수행 특성에 내재되어 있는 시간적 (temporal locality) 지역성과 공간적 지역성(spatial locality)을 활용하는 것이다. 본 논문은 프로그램 수행 특성에 적합한 시간적/공간적 지역성을 이용하기 위한 뱅크 선택 메커니즘을 가진 고성능 저전력 캐쉬 구조를 제안하였다. 제안하는 캐쉬 시스템은 다른 블록 크기와 다른 연관도를 가지는 두개의 캐쉬로 구성되어 진다. 즉 작은 블록 크기를 지원하는 직접사상 구조의 주 캐쉬(main direct-mapped cache)와 큰 블록을 지원하는 완전연관 버퍼 (fully associative buffer)로 구성되어 진다. 특히 주 캐쉬는 저전력을 위해 2-뱅크로 구성되며, 완전연관 버퍼에서 선택되어진 작은 블록은 제안된 뱅크 선택 알고리즘에 의해 주 캐쉬의 뱅크에 저장된다. 제안된 뱅크 선택 알고리즘과 3비트 상태 비트를 이용하여 시간적 지역성이 높은 데이터들을 주 캐쉬에 선택적으로 저장함으로써 고성능의 효과를 얻을 수 있었다. 제안된 알고리즘은 또한 충돌 미스 (conflict miss)와 캐쉬 오염 (cache pollution)을 효과적으로 줄여준다. 시뮬레이션 결과에 따르면, 평균 접근 실패율의 경우 Mibench 응용군에 대해 Victim 캐쉬에 비해 23%, STAS 캐쉬에 비해 32%의 감소효과를 보여준다. 평균 메모리 접근 시간의 경우 Victim 캐쉬에 비해 14%, STAS 캐쉬에 비해 18%의 감소효과를 얻을 수 있었다. 에너지 소비의 관점에서도 제안된 캐쉬 시스템은 Victim 캐쉬와 STAS 캐쉬에 비해 약 10% 감소 효과를 얻을 수 있었다. One of the most effective way to improve cache performance is to exploit both temporal and spatial locality given by any program executive characteristics. In this paper we present a high performance and low power cache structure with a bank selection mechanism that enhances exploitation of spatial and temporal locality. The proposed cache system consists of two parts, i.e., a main direct-mapped cache with a small block size and a fully associative buffer with a large block size as a multiple of the small block size. Especially, the main direct-mapped cache is constructed as two banks for low power consumption and stores a small block which is selected from fully associative buffer by the proposed bank selection algorithm. By using the bank selection algorithm and three state bits, We selectively extend the lifetime of those small blocks with high temporal locality by storing them in the main direct-mapped caches. This approach effectively reduces conflict misses and cache pollution at the same time. According to the simulation results, the average miss ratio, compared with the Victim and STAS caches with the same size, is improved by about 23% and 32% for Mibench applications respectively. The average memory access time is reduced by about 14% and 18% compared with the he victim and STAS caches respectively. It is also shown that energy consumption of the proposed cache is around 10% lower than other cache systems that we examine.

다양한 메모리 셀을 결합한 디스크형 플래쉬 메모리 시스템

정보성,이정훈,Jung, Bo-Sung,Lee, Jung-Hoon 대한임베디드공학회 2009 대한임베디드공학회논문지 Vol.4 No.3

We present a flash memory system with low cost and high performance for solid-state disk. The proposed flash system is constructed as a SLC with hot blocks and a MLC with cold blocks. Either the SLC or the MLC is selectively accessed on the basis of a position bit in a mapping table. Our results show that the system enables the SLC size to be reduced by about 80% relative to a conventional SLC while maintaining similar performance. And also, our system can improve a performance by above 60% comparing with a conventional MLC.

하드디스크 대용을 위한 공간적 스마트 버퍼 플래시 메모리 시스템

정보성(Bo-Sung Jung),이정훈(Jung-Hoon Jung) 한국컴퓨터정보학회 2009 韓國컴퓨터情報學會論文誌 Vol.14 No.3

플래시 메모리는 저전력, 저렴한 가격, 그리고 대용량저장매체로 그 중요성 및 수요에 대한 요구가 증대되고 있다. 이 연구는 하드디스크 대용을 위한 플래시 메모리 시스템을 구현하기 위하여 공간적 스마트 버퍼시스템을 통한 적극적인 공간적 지역성의 동적 페칭으로 고성능 플래시 메모리 설계에 목적이 있다. 제안된 플래시 메모리 시스템은 시간적 지역성을 위한 희생 버퍼, 공간적 지역성을 위한 공간적 버퍼 그리고 동적 페칭 유닛으로 이루어져 있다. 우리는 적극적인 동적 페칭을 위해 새로운 페칭 알고리즘을 제안한다. 즉, 새로운 구조와 새로운 알고리즘을 통하여 하드디스크 대용의 플래시 메모리 사용시 고려되어져 야 할 플래시 메모리의 단점을 줄여 범용 및 미디어 응용군에서 모두 고성능 효과를 이룰 수 있었다. 시뮬레이션 결과평균 접근실패율의 경우 미디어 응용군에 대해 기존의 스마트 버퍼시스템에 비해 25%감소 효과를 얻을 수 있었고, 평균 메모리 접근 시간의 경우스마트 버퍼시스템에 비해 35% 감소 효과를 얻을 수 있었다. 일반 범용 응용군에서도 30% 이상의 향상된 평균 메모리 접근 시간을 보였다. Flash memory has become increasingly requestion for the importance and the demand as a storage due to its low power consumption, cheap prices and large capacity medium. This research is to design a high performance flash memory structure for the substitution of a hard-disk by dynamic prefetching of aggressive spatial locality from the spatial smart buffer system. The proposed buffer system in a NAND flash memory consists of three parts, i.e., a fully associative victim buffer for temporal locality, a fully associative spatial buffer for spatial locality, and a dynamic fetching unit. We proposed new dynamic prefetching algorithm for aggressive spatial locality. That is to use the flash memory instead of the hard disk, the proposed flash system can achieve better performance gain by overcoming many drawbacks of the flash memory by the new structure and the new algorithm. According to the simulation results, compared with the smart buffer system, the average miss ratio is reduced about 26% for Mediabench applications. The average memory access times are improved about 35% for Mediabench applications, over 30% for Spec2000 applications.