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The Impedance Analysis of Multiple TSV-to-TSV
Sihyun Lee(이시현) 대한전자공학회 2016 전자공학회논문지 Vol.53 No.7
본 논문에서는 기존의 2D IC의 성능을 개선하고 3D IC의 집적도와 전기적인 특성을 개선하기 위한 목적으로 연구되고 있는 TSV (Through Silicon Via)의 임피던스를 해석하였다. 향후 Full-chip 3D IC 시스템 설계에서 TSV는 매우 중요한 기술이며, 높은 집적도와 광대역폭 시스템 설계를 위해서 TSV에 대한 전기적인 특성에 관한 연구가 매우 중요하다. 따라서 본 연구에서는 Full-chip 3D IC를 설계하기 위한 목적으로 다중 TSV-to-TSV에서 거리와 주파수에 따른 TSV의 임피던스 영향을 해석하였다. 또한 이 연구 결과는 Full-chip 3D IC를 제조하기 위한 반도체 공정과 설계 툴에 적용할 수 있다. In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.
Analysis on temperature dependent current mechanism of tunnel field-effect transistors
Lee, Junil,Kwon, Dae Woong,Kim, Hyun Woo,Kim, Jang Hyun,Park, Euyhwan,Park, Taehyung,Kim, Sihyun,Lee, Ryoongbin,Lee, Jong-Ho,Park, Byung-Gook IOP Publishing 2016 Japanese journal of applied physics Vol.55 No.6
<P>In this paper, the total drain current (I-D) of a tunnel FET (TFET) is decomposed into each current component with different origins to analyze the ID formation mechanisms of the TFET as a function of gate voltage (V-GS). Transfer characteristics are firstly extracted with fabricated Silicon channel TFETs (Si TFETs) and silicon germanium channel TFETs (SiGe TFETs) at various temperatures. The subthreshold swings (SS) of both Si TFETs and SiGe TFETs get degraded and the SSs of SiGe TFETs get degraded more as temperature becomes higher. Then, all the I(D)s measured at various temperatures are decomposed into each current component through technology computer aided design (TCAD) simulations with a good agreement with experimental data. As a result, it is revealed that Shockley-Read-Hall (SRH) recombination mainly contribute to the I-D of a TFET before band to band tunneling (BTBT) occurs. Furthermore, the SS degradation by high temperature is explained successfully by the SRH recombination with electric field dependence. (C) 2016 The Japan Society of Applied Physics</P>
The Fundamental Functionality Design of a Smart Farm Using an Embedded Computing Platform
Sihyun Lee(이시현) 대한전자공학회 2018 전자공학회논문지 Vol.55 No.4
본 논문에서는 2개의 범용 임베디드 컴퓨팅 플랫폼을 사용하여 사용자의 요구사항을 용이하게 적용하고 시장 적기성과 시스템의 유연성을 높이기 위한 목적으로 스마트 팜에 요구되는 기본적인 기능을 설계하였다. 2개의 임베디드 컴퓨팅 플랫폼을 사용한 스마트 팜 시스템은 주(master)-종(slave) 관계로 동작되는 구조이다. 주 임베디드 컴퓨팅 플랫폼은 ALTERA의 DE10-Nano(ARM Cortex-A9 프로세서 사용)을 사용하였으며, 종 임베디드 컴퓨팅 플랫폼은 STM32F407G-DISC1(ARM Cortex-M4) 임베디드 컴퓨팅 플랫폼을 사용하였다. 종 임베디드 컴퓨팅 플랫폼은 스마트 팜의 센서 및 모터 제어 등의 기본기능을 컨트롤하고 주임베디드 컴퓨팅 플랫폼과 통신기능을 수행한다. 본 논문에서 설계한 시스템은 스마트 팜 뿐만 아니라 특정한 응용분야에 적용할 경우 시스템의 시장 적기성, 시스템의 유연성 및 확장성을 가져올 수 있다. 향후 연구내용은 설계한 시스템에서 OpenCL 환경에서 전체 시스템의 성능 및 처리 속도를 향상할 수 있도록 DE10-Nano의 ARM Cortex-A9 프로세서와 FPGA 영역에서 3개의 32비트 RISC FPGA 소프트 코어 NiosII 프로세서를 사용하여 다중프로세서 시스템으로 설계하는 것이다. In this paper, we designed the fundamental functions required for smart farms for the purpose of applying user"s requirements easily using two general-purpose embedded computing platforms, and improving time-to-market and system flexibility. The smart farm system using two embedded computing platforms is designed as a system structure that operates in master-slave relationship. The master embedded computing platform used was ALTERA"s DE10-Nano using the ARM Cortex-A9 and the slave embedded computing platform used the STM32F407G-DISC1 (using the ARM Cortex-M4) embedded computing platform. The slave embedded computing platform controls fundamental functionalities such as sensor and motor control in smart farm and communicates with the master embedded computing platform. Therefore, the system designed in this paper can bring about marketability, system flexibility, and scalability of the system when applied not only to smart farm but also to specific application fields. Future work will be to improve the performance and processing speed of the entire system in the OpenCL (Open Computing Language) environment to apply the big data required in the intelligent farm system in the designed system. The ARM Cortex-A9 processor of the DE10-Nano will be used as the master processor, and the FPGA (Field Programmable Gate Array) area will be designed as a multiprocessor system using three 32bit RISC (Reduced Instruction Set Computer) FPGA soft core NiosII processors.
Kim, Sihyun,Kwon, Dae Woong,Park, Euyhwan,Lee, Junil,Lee, Roongbin,Lee, Jong-Ho,Park, Byung-Gook Elsevier 2018 Solid-state electronics Vol.140 No.-
<P><B>Abstract</B></P> <P>Numerous researches for making steep tunnel junction within tunnel field-effect transistor (TFET) have been conducted. One of the ways to make an abrupt junction is source/drain silicidation, which uses the phenomenon often called silicide-induced-dopant-segregation. It is revealed that the silicide process not only helps dopants to pile up adjacent to the metal-silicon alloy, also induces the dopant activation, thereby making it possible to avoid additional high temperature process. In this report, the availability of dopant activation induced by metal silicide process was thoroughly investigated by diode measurement and device simulation. Metal-silicon (MS) diodes having p<SUP>+</SUP> and n<SUP>+</SUP> silicon formed on the p<SUP>-</SUP> substrate exhibit the characteristics of ohmic and pn diodes respectively, for both the samples with and without high temperature annealing. The device simulation for TFETs with dopant-segregated source was also conducted, which verified enhanced DC performance.</P>
Crack-healing behavior of CVD grown silicon carbide
Pete Sihyun Lee,Hee-Jun Lee,김현미,김성훈,박재화,심광보 한양대학교 세라믹연구소 2016 Journal of Ceramic Processing Research Vol.17 No.7
CVD grown silicon carbide is ideal performance material for silicon wafer processing. It outperforms conventional forms ofsilicon carbide, as well as other ceramics, quartz, and metals. The combination of excellent thermal, electrical, and chemicalproperties makes this material well-suited to applications for RTP, epi, etch, implant, and across various industries where ahigh performance material requires. CVD SiC ceramics are brittle and sensitive to flaws. As a result, the structural integrityof ceramic component may be seriously affected. Crack- healing ability of CVD SiC ceramics is a very useful technology forhigher structural integrity and for reducing the machining and non-destructive inspection costs. This study focuses on CVDSiC ceramic performance and its crack-healing behaviors were investigated as a function of crack-healing temperature, time,size, and temperature dependence of the resultant bending strength. Three-point bending specimens were made and a semiellipticalcrack was introduced on the specimen by a Vickers indenter. Pre-cracked specimens were healed at varioustemperature conditions. The main conclusions were: (1) CVD grown SiC has cubic β‚ structure, it offers isotropiccharacteristics. (2) Optimized crack-healing condition is; temperature: 1500 oC, 1 hr in air. (3) The bending strength isincreased as testing temperature increased, means the material can be safely used up to a temperature of 1500 oC with a goodretention of thermal and mechanical properties.