http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : BUI CHINH HIEN (검색결과 1 건)
-
온칩 커뮤니케이션용 등화기능을 갖는 고속 직병렬 데이터 전송회로 설계
BUI CHINH HIEN 충북대학교 대학원 2013 국내석사
This thesis presents a wave-pipelined (WP) serializer - deserializer (SerDes) with asynchronous protocols and equalizers for high speed serial on-chip communications. The proposed equalization scheme consists of a 4-tap pre-emphasis or feedforward equalizer at the transmitter side and a 2-tap decision feed-back equalizer at the receiver side. A differential global on-chip interconnect pair is modeled and analyzed in a 3-D EM field solver to estimate the interconnect loss. Parameters of the target differential interconnect pair are 10-mm long, 0.5-μm thick, and 0.5-μm spacing. It is implemented on metal 5 layer in 130 nm CMOS process. A program built in Matlab is used to calculate equalizer parameters. Simulation results show that the proposed scheme can compensate for the intersymbol interference and the loss of the interconnects mentioned above at data rate up to 4Gb/s which is enabled by the proposed WP SerDes. Power consumption of the proposed WP SerDes with equalizers is 10 mW. Energy of the proposed equalizers is 2.45 pJ/bit. Using asynchronous protocols, the proposed WP SerDes reduces power consumption and circuit complexity compared with the conventional synchronous SerDes. The equalizers make the transmitted signals realizable after travelling through the lossy on-chip interconnects. The proposed WP SerDes can be applied in SoC or mobile applications that require high-speed and low-power on-chip communications.
연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
