Computer architecture

목차 (Table of Contents)

• CONTENTS
• PREFACE TO THIRD EDITION = ⅸ
• PREFACE TO SECOND EDITION = xi
• PREFACE TO FIRST EDITION = xiii
• 1 GATES AND ELEMENTARY LOGIC = 1
• Black Boxes = 2
• Synthesis of Black Boxes = 8
• Three-State Circuits = 10
• Flip-Flops = 12
• D-Type Flip-Flop = 16
• J-K Flip-Flop = 18
• Master-Slave Flip-Flop = 18
• Other Packaged Circuits = 18
• Levels of Integration = 19
• Transfer of Information = 22
• Multiple Pathways = 23
• Summary = 24
• 2 STORAGE MECHANISMS = 25
• Magnetic Cores = 25
• Magnetic Bubbles = 29
• Magnetic Recording = 35
• Semiconductors = 37
• Charge Coupled Devices = 43
• Read Only Memories = 45
• Mask Programmable ROM = 46
• Electrically Programmable ROM's = 47
• Reprogrammable ROM's = 47
• Summary = 48
• 3 PUTTING THE BITS TOGETHER = 49
• Co-Ordinate Address Storage = 49
• Word-Oriented Memories = 50
• Bit-Oriented Memories = 56
• Content Addressable Storage = 60
• The Comparison = 60
• Organization of a Content Addressable Memory = 62
• Match Circuits = 63
• Control Circuits = 63
• Read-Write Circuits = 64
• Priority Network = 64
• Pushdown Stacks = 67
• A Notation for Stack Operations = 69
• Implementation of Pushdown Stacks = 70
• Shift Registers = 70
• Pointer Implemented Pushdown Stacks = 73
• Linked List Stacks = 76
• Local Pointers = 78
• Insert and Delete = 79
• Implementation of a Linked List Stack = 80
• Moving Magnetic Memories = 83
• Drums = 84
• Moving Head Disks = 86
• Floppy Disks = 87
• Magnetic Tape = 89
• A CCD Memory = 89
• 4 AN ELEMENTARY MACHINE = 93
• A Programmer's Description = 93
• The Instruction Set = 94
• The Basic Machine Cycle = 97
• Information Flow in BLUE = 98
• Implementation of a Common Bus Scheme = 101
• Circuit Elements for BLUE = 101
• Control Unit = 103
• The Fetch Cycle = 107
• Input／Output Instructions = 108
• Memory Reference Instructions = 112
• The Arithmetic Unit = 114
• Circuits of the Control Unit = 119
• Summary = 122
• 5 VARIATIONS IN ALU DESIGN = 125
• Carry Lookahead Addition = 125
• Multiplication = 131
• Add and Shift Method = 131
• Using Carry Save Adders = 136
• Division = 141
• Restoring Algorithm = 141
• Nonrestoring Algorithm = 144
• Summary = 147
• 6 VARIATIONS IN ADDRESSING
• Four, Three, Two, One, Zero = 149
• Variable Length Op-codes = 150
• Variable Length Instructions = 153
• Short Form of Absolute Addressing = 154
• Indexing = 156
• Indirect Addressing = 159
• Base Registers = 162
• Pure Procedures = 164
• Paging = 166
• Short Address Paging = 166
• Banking = 167
• Paging in a Hierarchical Storage = 167
• Segmentation = 173
• Protection in a Multi-User Environment = 173
• Design 1 - The Fence = 174
• Discussion = 175
• Design 2 - The Bounds Registers = 175
• Discussion = 176
• Design 3 - Relocation-limit Registers = 177
• Summary = 178
• 7 VARIATIONS IN INPUT／OUTPUT = 180
• Programmed I／O = 180
• Interfacing to Slow Memories = 181
• Interrupts = 182
• Vectored Interrupts = 184
• Interrupts by Instruction Replacement = 188
• Semi-Autonomous Data Channels = 190
• Cycle Stealing = 196
• Variations = 196
• Peripheral Computers = 197
• Handshaking = 198
• Memory Mapped I／O = 202
• Summary = 203
• 8 OTHER INSTRUCTIONS = 204
• Byte Manipulation Instructions = 205
• Search Instructions = 207
• Pushdown Stacks = 209
• Microprogramming = 211
• Microprogrammed Version of BLUE = 212
• Master Reset = 212
• Branch on Op-code = 212
• Test Condition = 213
• Simulation of BLUE = 215
• Extensions to Micro BLUE = 220
• Microprogramming Using PLA's = 221
• Firmware versus Hardware = 222
• Summary = 222
• 9 MICROPROCESSORS AND MICROCOMPUTERS = 224
• What Is a Microprocessor? = 224
• Architecture of Microprocessors = 226
• Internal Interconnect Structure = 226
• Word Size = 228
• Instruction Formats for Limited Word Sizes = 228
• Control Unit = 229
• Pinout - How to Connect or the Outside World = 230
• Single-Chip Microcomputers = 234
• TI TMS1OOO Family = 234
• Zilog Z8 = 237
• Eight-bit Microprocessors = 243
• MOS Technology 6502 = 243
• Sixteen-bit Microprocessors = 248
• Intel-8086-80286 = 249
• BLUE as a Microprocessor = 254
• The Future of Microprocessors = 257
• 10 VERY LARGE COMPUTERS = 260
• Computer Classifications = 260
• SISD = 261
• SIMD = 262
• MISD = 262
• MIMD = 262
• Increasing Memory Speeds = 263
• Multiple Blocks = 263
• Wide Words = 264
• Caches and Buffers = 264
• Instruction Decode Overlap = 269
• Merry-Go-Round Designs = 271
• The PPU's of the 6600 = 272
• The Honeywell 8200 = 273
• The Edinburgh Design = 274
• Stacking Memory References = 275
• Loader = 277
• Saver = 277
• Further Details of the Design Process = 277
• Dedicated I／O Devices = 280
• Case Ⅰ : Cheap Register Groups = 280
• Case Ⅱ : Expensive Register Groups = 281
• Backing Store = 281
• Method Ⅰ : Fast Buffer Store = 281
• Method Ⅱ : Preemptive Demand = 282
• Multiple Functional Units = 283
• Pipelining = 284
• Summary = 287
• 11 PARALLELISM AND DISTRIBUTED LOGIC = 290
• Early Designs = 290
• Later Designs for Multiprocessing = 294
• C.mmp = 294
• IBM 370／1168MP and IBM 3033 = 297
• Fault Tolerance = 300
• Tandem NonStop Ⅱ = 302
• Networks = 305
• Local Area Networks = 307
• Long-Haul Networks = 314
• Distributed Logic = 315
• CACS-Ⅰ = 316
• Parallel Addition = 319
• CACS-Ⅱ = 321
• Multiple Tags = 321
• Shifts = 323
• Input／Output = 325
• Response Counting = 326
• Staran = 328
• 12 TESSELLATED COMPUTERS = 332
• The Computer with 29 States = 332
• Transient States = 333
• Transmission States = 334
• Confluent States = 335
• A Very Brief Outline of the Self-Reproducing Automation = 337
• Holland's Iterative Circuit Computer = 337
• Comments on the Holland Machine = 340
• The N-Cube Holland Machine = 340
• Hypercube = 341
• The Redefinable Neighborhood = 341
• Residence of Control = 342
• Accessing Remote Cells = 342
• The ORC = 343
• Illiac Ⅳ = 347
• APPENDIX A : THE REPRESENTATION OF INFORMATION = 349
• Binary Numbers = 350
• Trinary Numbers = 352
• Some Other Methods = 353
• Negative Numbers = 356
• Modular Arithmetic = 356
• Radix Complement = 357
• Diminished Radix Complement = 360
• NonIntegers = 362
• Fixed Point = 363
• Floating Point = 363
• Other Schemes of Representing Numbers = 367
• Codes for Decimal Digits = 368
• Nonnumeric Representations = 370
• Parity Bits = 371
• Residue Number Systems = 373
• INDEX = 377