Highly compact and accurate circuit-level macro modeling of charge-trap flash memory

다국어 초록 (Multilingual Abstract)

Charge-trap flash (CTF) memories are considered to represent the promising alternative in order for eventually replacing the floating-gate (FG) flash memory technologies in the near future owing to its higher device scalability and are targeted by developments of the most recent three-dimensional (3D) array architectures indeed. Various device structures and charge trapping layer materials have been adopted for advancing the CTF memories and different physical mechanisms have been closely studied in the respective cell operations.
In this paper, a highly compact and accurate circuit model of CTF memory cell is proposed, in consideration of the transient behaviors for describing the program operations. Although several compact models have been reported in the previous literature, the time-dependent behaviors of CTF cell have not been precisely reflected in the past models and the discrepancy between modeling and empirical results gets worse as the operation time elapses. The proposed circuit-level macro model in this work simply consists of one transistor, one voltage-controlled capacitor (VCCAP), and one voltage-controlled current source (VCCS) where the transient behaviors are mathematically embedded, with the improved compactness by reducing the number of current sources in the previous works. For expecting higher credibility of the developed SPICE models, they are verified by the measurement results from the fabricated CTF memory devices having the silicon-oxide-nitride-oxide-silicon (SONOS) stack under various operating conditions, by which plausible agreements between modeling and measurement results are demonstrated. Our more realistic circuit-level macro model would be practical and beneficial in designing the high-density 2D and 3D memory array and system architectures for 3D CTF memory. In particular, the results in this work should be significant when more accurate prediction of rigorous management of very narrow cell threshold voltage (Vt) window is indispensable for multi-level cell (MLC) and higher-level cell (XLC) operations.

목차 (Table of Contents)

• Chaper 1. Introduction 1
• 1.1 Flash Memory Technology 1
• 1.2 NOR and NAND Array Architecture 7
• 1.3 NAND Cell Operation 8
• Chapter 2. Scaling of NAND Flash Memory 11
• 2.1 Obstacles in NAND Flash Scaling 11
• 2.2 Multi-Bit Cell Storage 14
• 2.3 Charge-Trap Flash Memory 16
• 2.4 3-D Stacked NAND Flash Memory 18
• Chapter 3. Macro Modeling of Flash Cell with Planar Structure 26
• 3.1 Introduction 26
• 3.2 Experimental Methods 29
• 3.2.1 Tunneling Mechanism 35
• 3.2.2 Charge Centroid 40
• 3.3 Programming Characteristics of CTF Device with Planar Structure 47
• 3.4 Conclusion 58
• Chapter 4. Macro Modeling of Flash Cell with Cylindrical Structure 59
• 4.1 Introduction 59
• 4.2 Experimental Methods 60
• 4.2.1 Modified Tunneling Mechanism 65
• 4.2.2 Modified Charge Centroid 67
• 4.3 Programming Characteristics of CTF Device with Cylindrical Structure 71
• 4.4 Conclusion 75
• Chapter 5. Macro Modeling of Flash Cell Array 77
• 5.1 Introduction 77
• 5.2 Simulation Results 78
• 5.3 Conclusion 80
• Chapter 6. Conclusion 83
• Appendix A. Relation between Charge Centroid and Threshold Voltage Shift 86
• Appendix B. Mathematical Induction of Threshold Voltage Shift through Charge Centroid 94
• Appendix C. Tunneling in the Silicon-Oxide-Nitride-Oxide-Silicon Structures 98
• Appendix D. Extraction of Charge Centroid 106
• Bibliography 114
• Abstract in Korean 122
• List of Publications 124