New hierarchical partitioning and performance-driven placement techniques for automatic design of application specific integrated circuits (ASICs) using standard cells have been developed. The new partitioning algorithm builds a hierarchical tree for ...
New hierarchical partitioning and performance-driven placement techniques for automatic design of application specific integrated circuits (ASICs) using standard cells have been developed. The new partitioning algorithm builds a hierarchical tree for a given circuit by using the gradual constraint-enforcing technique. The new placement method performs truly hierarchical simulated-annealing based placements. When compared with several conventional partitioning and placement methods, the new methods produced favorable results for several benchmark examples.