In this paper, 32-bit pipelined RISC-type processor is designed and simulated with VHDL. The proposed datapath is designed from the result of analyzing the operations of unit functional block and each instruction.
Especially, forwarding and guarding...
In this paper, 32-bit pipelined RISC-type processor is designed and simulated with VHDL. The proposed datapath is designed from the result of analyzing the operations of unit functional block and each instruction.
Especially, forwarding and guarding unit is implemented for the purpose of resolving the various hazards.
Simulation is performed with V-system, Model Technology and Galileo, Examplar Logic.