In this paper, A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described, This stochastic architecture provides massive parallelism since stochastic logic is very space efficient and reprog...
In this paper, A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described, This stochastic architecture provides massive parallelism since stochastic logic is very space efficient and reprogrammability since synaptic weights are stored in digital shift register and large dynamic range by using either fixed or floating point weights and high execution speeds about N·108 connections per second and expandability by cascading of multiple chips to host large networks and practicality by building with CMOS device technologies.
results of simulations are given which show the stochastic architecture give results similar to those found using standard analog neural networks.