대기상태인 논리 회로에서의 누설전류 최소화 입력 탐색 방법 = Low Leakage Input Vector Searching Techniques for Logic Circuits at Standby States

목차 (Table of Contents)

• 요약
• Abstract
• Ⅰ. 서론
• Ⅱ. Leakage Minimization by Input vector Control (LMIC)
• Ⅲ. 실험
• Ⅳ. 결론
• 참고문헌
• 저자소개

참고문헌 (Reference)

1 J. Wenjie, "Topological analysis for leakage prediction of digital circuits" 39-44, 2002

2 A. Abdollahi, "Runtime mechanisms for leakage current reduction in CMOS VLSI circuits" 213-218, 2002

3 M. Johnson, "Models and Algorithms for bounds in CMOS Circuits" 18 (18): 714-725, 1999

4 Y. Kim, "Minimization of Leakage Current by Using the Genetic Algorithm" 190-194, 2005

5 K. Chopra, "Implicit Pseudo Boolean Enumeration Algorithms for Input Vector Control" 7-11, 2004

6 J. Halter, "Gate-Level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits" 475-478, 1997

7 F. Gao, "Exact and heuristic approaches to input vector control for leakage power reduction" 527-532, 2004

8 C. Zhanping, "Estimation of standby leakage power in CMOS circuit considering accurate modeling of transistor stacks" 239-244, 1998

9 B. Chatterjee, "Effectiveness and Scaling Trends of Leakage Control Techniques for Sub-130nm CMOS Technology" 25-27, 2003

10 A. Chandrakasan, "Design of High Performance Microprocessor Circuits" IEEE Press 2000

11 L. Wei, "Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits" 489-494, 1998