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      SCOPUS KCI등재

      Copper Seed Layer 형성 및 도금 첨가제에 따른 Copper Via Filling = Formation of Copper Seed Layers and Copper Via Filling with Various Additives

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      https://www.riss.kr/link?id=A105149590

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      다국어 초록 (Multilingual Abstract)

      Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.
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      Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a...

      Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

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      참고문헌 (Reference)

      1 T. Kobayashi, 47 : 85-, 2001

      2 K. Takahashi, 40 : 3032-, 2001

      3 P. C. Andricacos, 42 : 567-, 1998

      4 A. J. Cobley, 37 : 15-, 2011

      5 S. Miura, 169-170 : 91-, 2003

      6 D. Josell, 149 (149): C637-, 2002

      7 M. S. Park, 31 : 466-, 2011

      8 C. H. Seah, 114 : 233-, 2001

      9 W. -P. Dow, 54 : 5894-, 2009

      10 P. P. Lau, 253 : 2357-, 2006

      1 T. Kobayashi, 47 : 85-, 2001

      2 K. Takahashi, 40 : 3032-, 2001

      3 P. C. Andricacos, 42 : 567-, 1998

      4 A. J. Cobley, 37 : 15-, 2011

      5 S. Miura, 169-170 : 91-, 2003

      6 D. Josell, 149 (149): C637-, 2002

      7 M. S. Park, 31 : 466-, 2011

      8 C. H. Seah, 114 : 233-, 2001

      9 W. -P. Dow, 54 : 5894-, 2009

      10 P. P. Lau, 253 : 2357-, 2006

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      공동연구자 (7)

      유사연구자 (20) 활용도상위20명

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2014-03-01 평가 SCOPUS 등재 (기타) KCI등재
      2011-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2009-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2007-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2005-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2002-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      1999-07-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.15 0.15 0.14
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.14 0.13 0.255 0.03
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