This paper presents a design of the accelerate circuit for the conversion of the vector font data into the bit-mapped image. Among the Bezier curve algorithm, the subdivision algorithm gives the good performance and easy hardware implementation. Th...
This paper presents a design of the accelerate circuit for the conversion of the vector font data into the bit-mapped image. Among the Bezier curve algorithm, the subdivision algorithm gives the good performance and easy hardware implementation. The sequencer is realized by the proprammable gate array and the processing unit is composed if EPLDs and TTL ICs.