Computer aided logical design with emphasis on VLSI

목차 (Table of Contents)

• CONTENTS
• CHAPTER 1 LOGICAL ANALYSIS = 1
• 1.1 LOGIC DESIGN WITH AND WITHOUT CAD TOOLS = 1
• 1.2 TRUTH FUNCTIONS = 3
• 1.3 BINARY CONNECTIVES = 5
• 1.4 EVALUATION OF TRUTH FUNCTIONS = 6
• 1.5 MANY-STATEMENT COMPOUNDS = 7
• 1.6 PHYSICAL REALIZATIONS = 8
• 1.7 FUNCTIONALLY COMPLETE SETS OF CONNECTIVES = 11
• CHAPTER 2 NUMBER SYSTEMS AND CODES = 16
• 2.1 INTRODUCTION = 16
• 2.2 CONVERSION BETWEEN BASES = 17
• 2.3 ARITHMETIC WITH BASES OTHER THAN 10 = 20
• 2.4 NEGATIVE NUMBERS = 21
• 2.5 CODING OF DECIMAL NUMBERS = 22
• 2.6 PARITY = 24
• 2.7 ERROR-DETECTING AND CORRECTING CODES = 26
• 2.8 HAMMING CODES = 28
• CHAPTER 3 FUNDAMENTAL THEOREMS OF BOOLEAN ALGEBRA = 32
• 3.1 POSTULATES = 32
• 3.2 TRUTH FUNCTIONAL CALCULUS AS A BOOLEAN ALAEBRA = 34
• 3.3 DUALITY = 34
• 3.4 FUNDAMENTAL THEOREMS OF BOOLEAN ALGEBRA = 35
• 3.5 SET THEORY AS AN EXAMPLE OF BOOLEAN ALGEBRA = 39
• 3.6 ALTERNATIVE DEFINITION OF A BOOLEAN ALGEBRA = 41
• 3.7 EXAMPLES OF BOOLEAN SIMPLIFICATION = 43
• 3.8 REMARKS ON SWTCHING FUNCTIONS = 48
• 3.9 SUMMARY = 50
• CHAPTER 4 LOGIC ELEMENT REALIZATION = 54
• 4.1 OVERVIEW = 54
• 4.2 LOGIC ELEMENT REALIZATION WITH IDEAL SWITCHES = 54
• 4.3 BIPOLAR DIODE-TRANSISTOR LOGIC = 57
• 4.4 SPEED AND DELAY IN LOGI CIRCUITS = 60
• 4.5 TWO MORE BIPOLAR LOGIC FAMILIES = 62
• 4.6 COMPUTER-AIDED DESIGN OF VLSI = 65
• 4.7 MOS SWITCH REVISITED = 66
• 4.8 STRUCTURE OF n-CHANNEL AND p-CHANNEL DEVICES = 68
• 4.9 NMOS AND CMOS LOGIC ELEMENTS = 69
• 4.10 PASS TRANSISTOR = 73
• 4.11 NOISE MARGIN = 75
• CHAPTER 5 MANIPULATION OF BOOLEAN EXPRESSIONS = 80
• 5.1 MOTIVATION = 80
• 5.2 TOW-LEVEL REALIZATIONS WITH NAND OR NOR GATES = 80
• 5.3 STANDARD FORMS OF BOOLEAN FUNCTIONS = 82
• 5.4 MINTERM AND MAXTERM DESIGNATION OF FUNCTIONS = 84
• 5.5 KARNAUGH MAP REPRESENTATION OF BOOLEAN FUNCTIONS = 86
• 5.6 SIMPLIFICATION OF FUNCTIONS ON KARNAUGH MAPS = 94
• 5.7 MAP MINIMIZATIONS OF PRODUCT-OF-SUMS EXPRESSIONS = 104
• 5.8 INCOMPLETELY SPECIFIED FUNCTIONS = 105
• 5.9 LOGIC HAZARDS = 109
• 5.10 ELIMINATION OF HAZARDS = 112
• 5.11 SHANNON'S EXPANSION THEOREM = 113
• CHAPTER 6 ALGORITHMS FOR OPTIMIZATION OF COMBINATIONAL LOGIC = 119
• 6.1 IMPACT OF LOGIC SYNTHESIS = 119
• 6.2 CUBICAL REPRESENTATION OF BOOLEAN FUNCTIONS = 119
• 6.3 DETERMENATION OF PRIME IMPLICANTS = 122
• 6.4 SELECTION OF OPTIMUM SET OF PRIME IMPLICANTS = 127
• 6.5 MULTIPLE-OUTPUT CIRCUITS = 133
• 6.6 PROGRAMMED LOGIC ARRAY = 134
• 6.7 MINIMIZATION OF MULTIPLE-OUTPUT FUNCTIONS = 136
• 6.8 MINIMIZATION STRATEGY WITHOUT THE PLA COST CRITERIA = 141
• 6.9 TABULAR DETERMINATION OF PRIME IMPLICANTS = 143
• 6.10 ESPRESSO = 144
• 6.11 FIELD PROGRAMMABLE COMBINATIONAL LOGIC ARRAYS = 152
• CHAPTER 7 VLSI REALIZATIONS OF COMBINATIONAL LOGIC = 164
• 7.1 INTRODUCTION = 164
• 7.2 PASS TRANSISTOR NETWORK REALIZATIONS = 165
• 7.3 STEERING OF 0, 1, $$X_i$$, AND $$X_i$$ TO THE OUTPUT = 170
• 7.4 TREE NETWORKS = 173
• 7.5 NEGATIVE GATE REALIZATIONS = 177
• 7.6 LOGIC DESIGN WITH CMOS STANDARD CELLS = 180
• 7.7 GATE ARRAYS AND STANDARD CELLS = 183
• 7.8 PRECHARGED CLOCKING OF CMOS COMBINATIONAL LOGIC = 184
• 7.9 PRECHARGED CMOS PLA = 189
• CHAPTER 8 MULTILEVEL LOGIC USING COMPLES(MSI) PARTS AND CELLS = 193
• 8.1 THE PLACE FOR COMPLEX PARTS AND CELLS = 193
• 8.2 DECODERS = 193
• 8.3 READ-ONLY MEMORY AS A LOGIC ELEMENT = 196
• 8.4 BINARY ADDER = 200
• 8.5 DESIGN WITH MULTIPLEXERS = 204
• 8.6 MORE THAN TWO-LEVEL REALIZATIONS WITH BASIC PRIMITIVES = 209
• 8.7 COMBINATIONA MSI PARTS AND CELLS = 211
• 8.8 MULTILEVEL LOGIC MANIPULATION AND OPTIMIZATION = 216
• CHAPTER 9 COMPONENTS OF SEQUENTIAL SYSTEMS = 226
• 9.1 SEQUENTIAL ACTIVITY = 226
• 9.2 MEMORY ELEMENTS = 227
• 9.3 WHY SEQUENTIAL CIRCUITS? = 231
• 9.4 A GENERAL MODEL FOR SEQUENTIAL CIRCUITS = 234
• 9.5 CLOCK-MODE SEQUENTIAL CIRCUITS = 234
• 9.6 SATISFYING THE CLOCK-MODE ASSUMPTION = 237
• 9.7 THE STANDARD EDGE-TRIGGERED D FLIP-FLOP = 239
• 9.8 CLOCK SKEW AND TWO-PHASE CLOCKING OF NMOS MEMORY ELEMENTS = 241
• 9.9 CONNECTING DATA TO NMOS BUSES = 244
• 9.10 CHARGE-SHARING = 245
• 9.11 STATIC CMOS MEMORY ELEMENTS = 247
• 9.12 A TRI-STATE CMOS BUS = 249
• 9.13 CONCLUSION = 249
• CHAPTER 10 SYNTHESIS OF CLOCK-MODE SEQUENTIAL CIRCUITS = 253
• 10.1 ANALYSIS OF A SEQUENTIAL CIRCUIT = 253
• 10.2 DESIGN PROCEDURE = 255
• 10.3 SYNTHESIS OF STATE DIAGRAMS = 256
• 10.4 FINITE MEMORY CIRCUITS = 259
• 10.5 EQUIVALENCE RELATIONS = 266
• 10.6 EQUIVALENT STATES AND CIRCUITS = 267
• 10.7 DETERMINATION OF CLASSES OF INDISTINGUISHABLE STATES = 269
• 10.8 SIMPLIFICATION BY IMPLICATION TABLES = 275
• 10.9 MEALY CIRCUITS AND MOORE CIRCUITS = 279
• 10.10 STATE ASSIGNMENT AND MEMORY ELEMENT INPUT EQUATIONS = 284
• 10.11 PARTIONING AND STATE ASSIGNMENT = 290
• 10.12 CONCLUSIONS = 298
• CHAPTER 11 VECTOR PROCESSES : DESCRIPTION AND REALIZATION = 305
• 11.1 DESCRIPTION OF MORE COMPLEX SYSTEMS = 305
• 11.2 STANDARD SYMBOLS FOR THE ASM CHART = 306
• 11.3 CLOCK INPUT CONTROL = 310
• 11.4 EXTENDED STATE TABLES = 313
• 11.5 THE EXTENDED ASM CHART AND DESIGN LANGUAGE REPRESENTATION = 315
• 11.6 WRITING THE AHPL DESCRIPTION = 317
• 11.7 VECTOR OPERATIONS = 323
• 11.8 AHPL MODULES = 326
• 11.9 CONDITIONAL TRANSFERS AND CONNECTIONS = 331
• 11.10 MOS REALIZATIONS OF RTL DESCRIPTIONS = 335
• 11.11 COMBINATIONAL LOGIC UNIT DESCRIPTIONS = 336
• 11.12 CONCLUSIONS = 341
• CHAPTER 12 VLSI REALIZATION OF DIGITAL SYSTEMS = 349
• 12.1 OVERVIEW = 349
• 12.2 ALTERNATIVE STRUCTURAL DESCRIPTIONS = 351
• 12.3 LEVELS OF DESCRIPTION = 357
• 12.4 UNSYNCHRONIZED INPUTS, SETUP TIME, AND LOGIC VALUE U = 362
• 12.5 STANDARD CELL CMOS LAYOUT AND DELAY MODEL = 366
• 12.6 TIMING ANALYSIS AND SIMULATION = 371
• 12.7 EVENT-DRIVEN GATE-LEVEL SIMULATION = 376
• 12.8 SWITCH-LEVEL SIMULATION = 379
• 12.9 PROGRAMMABLE LOGIC DEVICES AND PROGRAMMABLE GATE ARRAYS = 386
• 12.10 SUMMARY = 389
• CHAPTER 13 INCOMPLETELY SPECIFIED SEQUENTIAL CIRCUITS = 396
• 13.1 INTRODUCTION = 396
• 13.2 COMPATIBILTIY = 398
• 13.3 REALIZATION OF SEQUENTIAL CIRCUITS WITH MANY DON'T CARES = 408
• 13.4 CONCLUSIONS = 410
• CHAPTER 14 LEVEL-MODE SEQUENTIAL CIRCUITS = 416
• 14.1 INTRODUCTION = 416
• 14.2 ANALYSIS OF A FUNDAMENTAL-MODE CIRCUIT = 418
• 14.3 DEVELOPING A FLOW TABLE = 419
• 14.4 MINIMIZATION = 421
• 14.5 TRANSITION TABLES, EXCITATION MAPS, AND OUTPUT MAPS = 427
• 14.6 CYCLES AND RACES = 429
• 14.7 RACE-FREE ASSIGNMENTS = 431
• 14.8 HAZARDS IN SEQUENTIAL CIRCUITS = 439
• 14.9 ELIMINATE THE FUNDAMENTAL-MODE RESTRICTION AT YOUR OWN RISK = 445
• CHAPTER 15 TEST GENERATION FOR VLSI = 456
• 15.1 FAULT DETECTION AND DIAGNOSIS = 456
• 15.2 STUCK-AT FAULT MODEL = 457
• 15.3 TEST GENERATION STRATEGY = 461
• 15.4 BOOLEAN DIFFERENCES = 463
• 15.5 TEST GENERATION BY EVALUATION AND SEARCH = 467
• 15.6 MODELING CMOS STUCK-OPEN FAULTS = 472
• 15.7 FAULT SIMULATION IN SEQUENTIAL SYSTEMS = 475
• 15.8 OBSERVABILITY, CONTROLLABILITY, AND SCAN PATHS = 478
• 15.9 BOUNDARY SCAN = 480
• 15.10 BUILT-IN SELF-TEST = 482
• CHAPTER 15 COMBINATIONAL LOGIC FUCTIONS WITH SPECIAL PROPERTIES = 490
• 16.1 INTRODUCTION = 490
• 16.2 SYMMETRIC FUNCTIONS = 490
• 16.3 BOOLEAN COMBINATIONS OF SYMMETRIC FUNCTIONS = 492
• 16.4 SIMPLE DISJOINT DECOMPOSITION = 494
• 16.5 COMPLEX DISJOINT DECOMPOSITION = 499
• 16.6 ITERATIVE NETWORKS = 506
• 16.7 TEST GENERATION USING THE ANALOGOUS ITERATIVE NETWORK = 510
• APPENDIX A SELECTION OF MINIMAL CLOSED COVERS = 517
• APPENDIX B SUMMARY OF AHPL SYNTAX = 524
• B.1 OPERAND CONVENTIONS = 524
• B.2 AHPL OPERATORS = 524
• B.3 AHPL MODULES = 526
• B.4 AHPL TRANSFER AND CONNECTION STATEMENTS = 527
• INDEX = 529