VLSI Detailed Router 개발에 관한 연구 = A Study on the Development of a Datailed channel Router for VLSI Layout Design

다국어 초록 (Multilingual Abstract)

This paper presents a rule-based channel router based on the routing rules and the two layer bidirectional scheme which is assigned both horizontal and vertical direction in each layer, in order to minimize the number of vias.
At first, to reduce the execution time, this router classifies the nets by the shape of nets and examines the cycle for the type C of net with both the in-directed edge and the out-directed edge. Secondly, if there exists the cycle, we select the net on the various conditions and route the other nets except the selected net. Finally, we find a dogleg-possible column and dogleg the net at the column.
The router proposed in this paper assigns as many nets as possible to a track to minimize the number of tracks and to reduce the wire length. The efficiency of this router is shown by the experiments with examples.

목차 (Table of Contents)

• Ⅰ. 서 론
• Ⅱ. 제한 그래프와 Cycle검출 및 제거
• Ⅲ. 채널 배선기
• Ⅳ. 실험결과
• Ⅴ. 결 론