DRAM의 성능 향상을 위한 Pre-Refresh 기법

다국어 초록 (Multilingual Abstract)

Dynamic random access memory (DRAM) latency depends on the row activation time required to detect the charge of a DRAM cell. If a DRAM cell is fully charged, the sense amplifier can rapidly detect charges, thus reduce the row activation time. In this paper, we propose a pre-refresh technique to reduce the row activation time of DRAM. The pre-refresh technique charges DRAM cells in a row that are expected to be accessed while DRAM is idle. If any DRAM cells in the row are read or written soon, the row activation time can be reduced. Experimental results show that, when the pre-refreshed quad-core processor performs PARSEC benchmarks, a memory system with the pre-refresh technique causes 5.49% less power consumption, and achieves 11.8% faster program execution time.

참고문헌 (Reference)

1 박태진, "병렬 TLC STT-MRAM 기반 대용량 LLC 설계" 한국정보기술학회 15 (15): 77-89, 2017

2 Lee, Donghyuk, "Tiered-latency DRAM: A low latency and low cost DRAM architecture" 615-626, 2013

3 Christian Bienia, "The PARSEC benchmark suite: Characterization and architectural implications" 72-81, 2008

4 Kalyan, T. Venkata, "Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time" 598-603, 2014

5 Venkatesan, Ravi K., "Retention-aware placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM" 157-167, 2006

6 Liu, Jamie, "RAIDR: Retention-aware intelligent DRAM refresh" 40 (40): 1-12, 2012

7 Wongyu Shin, "NUAT: A non-uniform access time memory controller" 464-465, 2014

8 Shen, John Paul, "Modern processor design: fundamentals of superscalar processors" Waveland Press 2013

9 Jacob, Bruce, "Memory systems: cache, DRAM, disk" Morgan Kaufmann 2010

10 Patel, Avadh, "Marss-x86: A qemu-based micro-architectural and systems simulator for x86 multicore processors" 2011

11 "JEDEC DDR3 standard"

12 Chen, I-Cheng K., "Instruction prefetching using branch prediction information" 593-603, 1997

13 Chang, Kevin Kai-Wei, "Improving DRAM performance by parallelizing refreshes with accesses" 356-367, 2014

14 Ishwar Bhati, "Flexible auto-refresh" Association for Computing Machinery (ACM) 43 (43): 235-246, 2016

15 Jeffrey Stuecheli, "Elastic refresh: Techniques to mitigate refresh penalties in high density memory" 375-384, 2010

16 Rosenfeld, Paul, "DRAMSim2: A cycle accurate memory system simulator" 10 (10): 16-19, 2011

17 Hassan, Hasan, "ChargeCache: Reducing DRAM latency by exploiting row access locality" 581-593, 2016