1 정보성, "저전력 집합연관 캐시를 위한 효과적인 알고리즘" 대한임베디드공학회 9 (9): 25-32, 2014
2 박태진, "병렬 TLC STT-MRAM 기반 대용량 LLC 설계" 한국정보기술학회 15 (15): 77-89, 2017
3 "https://software.intel.com/sites/landingpage/pintool/docs/81205/Pin/html/"
4 P.M. Palangappa, "WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory" 64 (64): 1028-1040, 2016
5 J. Kin, "The Filter Cache: An Energy Efficient Memory Structure" 184-193, 1997
6 J. Li, "STT-RAM Based Energy-Efficiency Hybrid Cache for CMPs" 31-36, 2011
7 J.W. Ahn, "Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture" 64 (64): 940-951, 2015
8 X. Wu, "Power and Performance of Read-Write Aware Hybrid Caches With Non-Volatile Memories" 737-742, 2009
9 Y. Meng, "On the Limits of Leakage Power Reduction in Caches" 154-165, 2005
10 M. Imani, "Low Power Data-Aware STT-RAM based Hybrid Cache Architecture" 88-94, 2016
1 정보성, "저전력 집합연관 캐시를 위한 효과적인 알고리즘" 대한임베디드공학회 9 (9): 25-32, 2014
2 박태진, "병렬 TLC STT-MRAM 기반 대용량 LLC 설계" 한국정보기술학회 15 (15): 77-89, 2017
3 "https://software.intel.com/sites/landingpage/pintool/docs/81205/Pin/html/"
4 P.M. Palangappa, "WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory" 64 (64): 1028-1040, 2016
5 J. Kin, "The Filter Cache: An Energy Efficient Memory Structure" 184-193, 1997
6 J. Li, "STT-RAM Based Energy-Efficiency Hybrid Cache for CMPs" 31-36, 2011
7 J.W. Ahn, "Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture" 64 (64): 940-951, 2015
8 X. Wu, "Power and Performance of Read-Write Aware Hybrid Caches With Non-Volatile Memories" 737-742, 2009
9 Y. Meng, "On the Limits of Leakage Power Reduction in Caches" 154-165, 2005
10 M. Imani, "Low Power Data-Aware STT-RAM based Hybrid Cache Architecture" 88-94, 2016
11 Z. Hu, "Let Cache Decay: Reducing Leakage Energy via Exploitationi of Cache Generational Behavior" 20 (20): 161-190, 2002
12 N.S. Kim, "Leakage Current: Moore's Law Meets Static Power" 36 (36): 68-75, 2003
13 "ITRS: International Technology Roadmap for Semiconductor, 2008 report"
14 A. Jadidi, "High-Endurance and Performance-Efficient Design of Hybrid Cache Architectures Through Adaptive Line Replacement" 79-84, 2011
15 S.P. Pack, "Future Cache Design Using STT-RAMs for Improved Energy Efficiency: Devices, Circuits and Architecture" 492-497, 2012
16 K. Flautner, "Drowsy Cache: Simple Techniques for Reducing Leakage Power" 148-157, 2002
17 N. Muralimanohar, "CACTI 6.0: A tool to model large caches" 22-31, 2009