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      고성능 저전력 하이브리드 L2 캐시 메모리를 위한 연관사상 집합 관리 = Way-set Associative Management for Low Power Hybrid L2 Cache Memory

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      https://www.riss.kr/link?id=A105453687

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      다국어 초록 (Multilingual Abstract)

      STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.
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      STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile ...

      STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

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      참고문헌 (Reference)

      1 정보성, "저전력 집합연관 캐시를 위한 효과적인 알고리즘" 대한임베디드공학회 9 (9): 25-32, 2014

      2 박태진, "병렬 TLC STT-MRAM 기반 대용량 LLC 설계" 한국정보기술학회 15 (15): 77-89, 2017

      3 "https://software.intel.com/sites/landingpage/pintool/docs/81205/Pin/html/"

      4 P.M. Palangappa, "WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory" 64 (64): 1028-1040, 2016

      5 J. Kin, "The Filter Cache: An Energy Efficient Memory Structure" 184-193, 1997

      6 J. Li, "STT-RAM Based Energy-Efficiency Hybrid Cache for CMPs" 31-36, 2011

      7 J.W. Ahn, "Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture" 64 (64): 940-951, 2015

      8 X. Wu, "Power and Performance of Read-Write Aware Hybrid Caches With Non-Volatile Memories" 737-742, 2009

      9 Y. Meng, "On the Limits of Leakage Power Reduction in Caches" 154-165, 2005

      10 M. Imani, "Low Power Data-Aware STT-RAM based Hybrid Cache Architecture" 88-94, 2016

      1 정보성, "저전력 집합연관 캐시를 위한 효과적인 알고리즘" 대한임베디드공학회 9 (9): 25-32, 2014

      2 박태진, "병렬 TLC STT-MRAM 기반 대용량 LLC 설계" 한국정보기술학회 15 (15): 77-89, 2017

      3 "https://software.intel.com/sites/landingpage/pintool/docs/81205/Pin/html/"

      4 P.M. Palangappa, "WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory" 64 (64): 1028-1040, 2016

      5 J. Kin, "The Filter Cache: An Energy Efficient Memory Structure" 184-193, 1997

      6 J. Li, "STT-RAM Based Energy-Efficiency Hybrid Cache for CMPs" 31-36, 2011

      7 J.W. Ahn, "Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture" 64 (64): 940-951, 2015

      8 X. Wu, "Power and Performance of Read-Write Aware Hybrid Caches With Non-Volatile Memories" 737-742, 2009

      9 Y. Meng, "On the Limits of Leakage Power Reduction in Caches" 154-165, 2005

      10 M. Imani, "Low Power Data-Aware STT-RAM based Hybrid Cache Architecture" 88-94, 2016

      11 Z. Hu, "Let Cache Decay: Reducing Leakage Energy via Exploitationi of Cache Generational Behavior" 20 (20): 161-190, 2002

      12 N.S. Kim, "Leakage Current: Moore's Law Meets Static Power" 36 (36): 68-75, 2003

      13 "ITRS: International Technology Roadmap for Semiconductor, 2008 report"

      14 A. Jadidi, "High-Endurance and Performance-Efficient Design of Hybrid Cache Architectures Through Adaptive Line Replacement" 79-84, 2011

      15 S.P. Pack, "Future Cache Design Using STT-RAMs for Improved Energy Efficiency: Devices, Circuits and Architecture" 492-497, 2012

      16 K. Flautner, "Drowsy Cache: Simple Techniques for Reducing Leakage Power" 148-157, 2002

      17 N. Muralimanohar, "CACTI 6.0: A tool to model large caches" 22-31, 2009

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2028 평가예정 재인증평가 신청대상 (재인증)
      2022-01-01 평가 등재학술지 유지 (재인증) KCI등재
      2019-01-01 평가 등재학술지 유지 (계속평가) KCI등재
      2016-01-01 평가 등재학술지 유지 (계속평가) KCI등재
      2014-07-03 학술지명변경 외국어명 : Journal of IEMEK -> IEMEK Journal of Embedded Systems and Applications KCI등재
      2012-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2011-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2009-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.27 0.27 0.22
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.22 0.18 0.415 0.07
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