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Variable ordering for regular layout representation
Chzanowska-Jeske, M.; Xu, Y. IEEE 1998 p.l.93-1.96
A 10-bit high-speed low-power CMOS D/A converter in 0.2 mm2
Sumanen, L.; Waltari, M.; Halonen, K. IEEE 1998 p.1.15-1.18
A 1.2 V rail-to-rail switched buffer
Ferri, G.; Costa, A.; Baschirotto, A. IEEE 1998 p.1.45-1.50
A 1.5V CMOS Voltage Multiplier
Giustolisi, G.; Palmisano, G.; Palumbo, G. IEEE 1998 p.1.313-1.316
An 1.8 V low-power CMOS high-speed four quadrant multiplier with rail-to-rail differential input
Lin, C.-H.; Ismail, M. IEEE 1998 p.1.37-1.40
A 3V, 10 bit, 6.4 MHz switched-current CMOS A/D converter design
Jonsson, B. E. IEEE 1998 p.1.27-1.32
A 48 by 48 CNN chip operating with B/W images
Paasio, A.; Kananen, A.; Halonen, K.; Porra, V. IEEE 1998 p.1.191-1.194
An, J. G.; Shim, J. S.; Kim, Y. M.; Lee, M. M.-O. IEEE 1998 p.1.463-1.466
A 64 x 64 CNN universal chip with analog and digital I/O
Li�n, G.; Espejo, S.; Domingos-Castro, R.; Roca, E. IEEE 1998 p.1.203-1.208