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    A fully integrated 2.4-GHz CMOS RF transceiver for low-rate wireless sensor networks

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    https://www.riss.kr/link?id=A107592120

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    <P>This article describes a low-power and low-cost fully integrated 2.4 GHz IEEE 802.15.4 RF transceiver for low-rate wireless sensor networks. The RF transceiver adopts the single-IF direct-conversion architecture. For the high linearity, the RF receiver front end utilizes the current mirror amplifier as well as the transconductance linearization technique. The single-IF I/Q modulation transmitter is integrated with the current-mode analog baseband circuit and up-mixer using the current mirror amplifier. The frequency synthesizer based on an integer-N PLL topology offering 1.92 GHz differential and 0.48 GHz quadrature LO signals is also integrated on the RF transceiver. The fully integrated transceiver is fabricated in a 0.18-μm CMOS technology and its die size is 3.7 mm × 3.6 mm including ESD I/O pads. It achieves the −94 dBm receiver sensitivity, 8 dB receiver chain noise figure, and maximum transmitter output power of 1 dBm while drawing power consumption of 31 mW in the receive mode and 42 mW in the transmit mode with the 1.8 V supply. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1481–1487, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24349</P>
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    <P>This article describes a low-power and low-cost fully integrated 2.4 GHz IEEE 802.15.4 RF transceiver for low-rate wireless sensor networks. The RF transceiver adopts the single-IF direct-conversion architecture. For the high linearity, the R...

    <P>This article describes a low-power and low-cost fully integrated 2.4 GHz IEEE 802.15.4 RF transceiver for low-rate wireless sensor networks. The RF transceiver adopts the single-IF direct-conversion architecture. For the high linearity, the RF receiver front end utilizes the current mirror amplifier as well as the transconductance linearization technique. The single-IF I/Q modulation transmitter is integrated with the current-mode analog baseband circuit and up-mixer using the current mirror amplifier. The frequency synthesizer based on an integer-N PLL topology offering 1.92 GHz differential and 0.48 GHz quadrature LO signals is also integrated on the RF transceiver. The fully integrated transceiver is fabricated in a 0.18-μm CMOS technology and its die size is 3.7 mm × 3.6 mm including ESD I/O pads. It achieves the −94 dBm receiver sensitivity, 8 dB receiver chain noise figure, and maximum transmitter output power of 1 dBm while drawing power consumption of 31 mW in the receive mode and 42 mW in the transmit mode with the 1.8 V supply. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1481–1487, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24349</P>

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