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Doping Challenges in Exploratory Devices for High Performance Logic
Jones, E. C. IEEE 2002 p.1-6
Source/Drain Engineering for Sub-100 nm Technology Node
Ohuchi, K.;Adachi, K.;Hokazono, A.;Toyoshima, Y. IEEE 2002 p.7-12
Yeh, K. S. Y.;Chiang, M. C.;Tsai, C. J.;Wang, Y. L.;Wang, J. K. IEEE 2002 p.13-16
Process Control Issues for Retrograde Well Implants for Narrow n^+/p^+ Isolation in CMOS
Rubin, L.;Morris, W.;Jasper, C. IEEE 2002 p.17-20
Optimizing P-Type Ultra-Shallow Junctions for the 65 nm CMOS Technology Node
Pawlak, B. J.;Lindsay, R.;Surdeanu, R.;Stolk, P.;Maex, K.;Pages, X. IEEE 2002 p.21-24
Boron Retarded Diffusion in the Presence of Indium or Germanium
Li, H.-J.;Kirichenko, T. A.;Kohli, P.;Banerjee, S. K.;Graetz, E.;Tichy, R.;Zeitzoff, P. IEEE 2002 p.25-28
Investigation of Indium Activation by SRP and SIMS for sub-0.1 mum Retrograde Channels
Suvkhanov, A.;Mirabedini, M.;Hornback, V.;Nitodas, S. F.;Kalnas, C. E.;Ye, C. W. IEEE 2002 p.29-32
Implanted-Ion Dose Variation from Si Surface Status of sub-nm Scale on 90 nm ULSI Process
Kase, M.;Kubo, T.;Watanabe, K.;Okabe, K.;Nakao, H. IEEE 2002 p.33-35
Fabrication of 60 nm Plasma-doped CMOS Transistors
Lenoble, D.;Grouillet, A.;Boeuf, F.;Skotnicki, T.;Hacker, D.;Scheuer, J.;Walther, S. IEEE 2002 p.36-39
Impact of Energy Contamination of Ultra-Low Energy Implants on Sub-0.1 mum CMOS Device Performance
Lenoble, D.;Prod homme, P.;Beutier, D.;Julien, C. IEEE 2002 p.40-43