As volatile and nonvolatile memory technologies evolve toward three-dimensional (3D) architectures with complex, high-aspect-ratio structures to achieve higher integration density, atomic layer deposition (ALD) has become an enabling technology for ad...
As volatile and nonvolatile memory technologies evolve toward three-dimensional (3D) architectures with complex, high-aspect-ratio structures to achieve higher integration density, atomic layer deposition (ALD) has become an enabling technology for advanced memory devices owing to its precise thickness controllability and excellent conformality under low-temperature processing constraints. This dissertation establishes ALD processes for oxide thin films relevant to advanced memory technologies and analyzes their physical and chemical properties in conjunction with the resulting electrical characteristics.
First, magnesium oxide (MgO), a high-k dielectric, was investigated as a potential blocking oxide material for charge-trap flash memory, a representative non-volatile memory device. An ALD process for MgO was established using a highly volatile Mg(EtCp)2 precursor and H2O as the oxidant. The film characteristics and dielectric properties required for blocking oxide applications, including step coverage, stoichiometry, leakage current, bandgap, conduction band offset with silicon, and dielectric constant, were evaluated. The performance of ALD-MgO was further benchmarked through a comparison with ALD-Al2O3, the most widely used blocking oxide material
Second, zinc tin oxide (ZTO) was investigated as an amorphous oxide semiconductor channel for 3D dynamic random-access memory (DRAM) applications. ALD processes for ZTO were developed using a super-cycle method confirming compositional controllability. Subsequently, the composition-dependent defect characteristics and crystallization temperature were examined. Top-gate thin-film transistors (TFTs) integrating ALD-deposited ZTO channels with ALD-grown HfO2 gate dielectrics were fabricated, and their electrical characteristics and reliability under various bias and bias-temperature stress conditions were evaluated; the dominant degradation mechanisms were discussed
Finally, the influence of the channel/bottom dielectric interface on the electrical characteristics of top-gate TFTs was systematically investigated. The intrinsic negative fixed charges associated with Al2O3 interfaces, together with interlayer diffusion behavior, were examined and interpreted in terms of their combined impact on electrical characteristics. It was observed that the electrical properties of the devices could be modulated without altering the channel or gate dielectric materials, and possible physical mechanisms underlying this behavior were discussed.