효율적인 재구성 가능한 DSP 구조 = An Efficient Reconfigurable DSP Architecture

다국어 초록 (Multilingual Abstract)

Modern DSP’s commonly run a set of complicated algorithms which take long run time and high power consumption. Accelerating IP’s are often employed to reduce the execution time and the power consumption. However, as the complexity and the variability of the DSP algorithms are growing, more and more accelerating IP’s are required. Since such specialized fixed IP’s are hard to design and debug, DSP’s with multiple accelerating IP’s are very likely to have a very poor time-to-market and an unacceptably high area cost. To improve the time-to-market and the area efficiency, dynamically reconfigurable DSP architectures have gained a lot of attention lately. Dynamically reconfigurable DSP’s typically have one (or two) multi-functional DSP accelerator which executes different, yet similar multiple core computations for a set of DSP algorithms. With this type of dynamically reconfigurable DSP accelerators, the time to market and the area/power efficiency of the DSP designs can be improved significantly.

목차 (Table of Contents)

• Abstract
• Ⅰ. 서론
• Ⅱ. Related Work
• Ⅲ. 재구성 가능한 DSP Accelerator
• Ⅳ. DSP 알고리즘
• Ⅴ. 실험결과
• Ⅵ. 결론
• 참고문헌