Stacked Single Crystal Silicon TFT Cell의 적용에 의한 SRAM 셀의 전기적인 특성에 관한 연구 = Electrical Characteristics of SRAM Cell with Stacked Single Crystal Silicon TFT Cell

다국어 초록 (Multilingual Abstract)

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

참고문헌 (Reference)

1 "Novel 3-dimensional 46 F2 SRAM technology with 0.294 um2 S3 (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)" 445-, 2004.

2 "Ion-implanted Ti poly crystalline- silicon high value resistor for high density poly load static RAM application" 32 : 1749-, 1985.

3 "HMOS ⅡStatic RAMs over- take bipolar competition" 52 : 124-, 1979.

4 "HMOS ⅡStatic RAMs over- take bipolar competition" 52 : 124-, 1979.

5 "Consideration of poly-si loaded cell capacity limits for low power and high-speed SRAMs" 683-, 1992.

6 "A coincident-select MOS storage array" 280-, 1968.

7 "A 40 ns 144 bit n-channel MOS LSI memory" 271-, 1969.