1 "나노구조 Double Gate MOSFET의 핀치오프특성에 관한 연구" 6 (6): 1074-1078, 2002.
2 "Study of SILC and Interface Trap Generation Due to High Field Stressing and Its Operating Temperature Dependence in 2.2㎚ Gate Dielectrics" 49 (49): 699-701, 2002
3 "Side-Gate Design Optimization of 50㎚ MOSFETs with Electrically Induced Source/Drain" 41 (41): 2345-2347, 2002
4 "Atomic-scale modeling of double gate MOSFETs using a tight- binding Green's function formalism" 48 : 567-574, 2004.
5 "An analytical solution to a double-gate MOSFET with undoped body" 21 : 245-247, 2000.
6 "Advanced Model Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime-Part I : Theoretical Derivation" 49 (49): 457-466, 2002
7 "A Continous, Analytic Drain-Current Model for DG MOSFETs" 25 : 107-109, 2004.
8 "70㎚ NMOSFET Fabrication with 12㎚ n+-p Junctions Using As2+ Low Energy Implantations" 40 (40): 2607-2610, 2001
1 "나노구조 Double Gate MOSFET의 핀치오프특성에 관한 연구" 6 (6): 1074-1078, 2002.
2 "Study of SILC and Interface Trap Generation Due to High Field Stressing and Its Operating Temperature Dependence in 2.2㎚ Gate Dielectrics" 49 (49): 699-701, 2002
3 "Side-Gate Design Optimization of 50㎚ MOSFETs with Electrically Induced Source/Drain" 41 (41): 2345-2347, 2002
4 "Atomic-scale modeling of double gate MOSFETs using a tight- binding Green's function formalism" 48 : 567-574, 2004.
5 "An analytical solution to a double-gate MOSFET with undoped body" 21 : 245-247, 2000.
6 "Advanced Model Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime-Part I : Theoretical Derivation" 49 (49): 457-466, 2002
7 "A Continous, Analytic Drain-Current Model for DG MOSFETs" 25 : 107-109, 2004.
8 "70㎚ NMOSFET Fabrication with 12㎚ n+-p Junctions Using As2+ Low Energy Implantations" 40 (40): 2607-2610, 2001