HDTV TS 패킷 전송을 위한 ATM 적응 레이어의 설계에 관한 연구 = A Study on Design of ATM Adaptation Layer for HDTV TS Packet Communication

다국어 초록 (Multilingual Abstract)

An improved ATM adaptation layer against the excessive packet loss or packet delay variation when HDTV 75 is transmitted over ATM network, is implemented with FPGA for its behavioral verification. The proposed ATM adaptation layer uses sequence numbering scheme for detection of existence and the location of the cell loss in the 75 packet. The usage of sequence numbering sheme enables the detection of the location of corrupted 75 packet, hence prevents an excessive packet loss and ensures higher packet receive rate at the receiver. The sequence numbering scheme also reduces the packet delay variation originated from cell loss or cell delay in ATM network, hence miss synchronization of HDTV transport stream by packet jitter at the HDTV decoder is prevented.
The proposed ATM adaptation layer is modeled using HDL. The modeled AAL is synthesized and Place&Routed using FPGA library. From the result o P&R, Standard Delay File(SDF) is extracted and used for post-layout simulation then the bit file is generated from the resu3ting netlist of post-layout simulation. Generated bit file is downloaded into FPGA and its behavior is verified using logic analyzer.

목차 (Table of Contents)

• Ⅰ.서론
• Ⅱ관련연구
• Ⅲ.CBR HDTV TS 패킷 전송을 위한 새로운 메카니즘의 제안
• Ⅳ.전송단 및 수신단의 하드웨어 구현
• Ⅴ.VHDL을 이용한 회로 설계 및 검증
• Ⅵ.FPGA를 통한 기능 검증
• Ⅶ.결론