5.4비트의 유효비트를 가지는 1V 1.6-GS/s 6비트 플래쉬 아날로그-디지털 변환기

다국어 초록 (Multilingual Abstract)

This paper proposes A 1V 1.6-GS/s 6-bit flash analog-to-digital converter(ADC). A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation and the dynamic performance of flash ADC is increased by adding a SR latch at the output node of each comparator. The proposed flash ADC is fabricated using a 90nm 1-poly 9-metal CMOS process with 1V supply. The measured DNL(Differential Non-linearity) and INL(Integral Non-linearity) are +0.56/-0.49 LSB(Least Significant Bit) and +0.74/-0.84 LSB, respectively. The measured SNDR(Signal-to-Noise and Distortion Ratio) and ENOB(Effective Number of Bits) are 34.3dB and 5.4 bit for a 800 MHz analog input signal. The ENOB of 0.3 bit was improved by the SR latch added at the output node of each comparator. The power consumption and chip area of flash ADC are 800×500μ㎡ and 399.3mW, respectively.

참고문헌 (Reference)

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