1 de Jong,E.C.W, "Toward the Next Level of PCB Usage in Power Electronic Converters" 23 (23): 3151-3163, 2008
2 Fu,G, "The relationship between wafer surface pressure and wafer backside loading in Chemical Mechanical Polishing" 474 (474): 217-221, 2005
3 Seo,Y.J, "Optimization of post-CMP cleaning process for elimination of CMP slurry-induced metallic contaminations" 12 (12): 411-415, 2001
4 Venkatesh,V.C, "Observations on Polishing and Ultraprecision Machining of Semiconductor Substrate Materials" 44 (44): 611-618, 1995
5 Wolf,M.J, "Flip chip bumping technology-Status and update" 565 (565): 290-295, 2006
6 Freudenberg Mektec Europa GmbH, "Flexible Printed Circuits Open Up a Multitude of Innovative Applications"
7 Du,T, "Effect of hydrogen peroxide on oxidation of copper in CMP slurries containing glycine and Cu ions" 49 (49): 4505-4512, 2004
8 Park,S.-W, "Design of experimental optimization for ULSI CMP process applications" 66 (66): 488-495, 2003
9 Monteith,M.P, "Components of within-wafer non-uniformity in a dielectric CMP process" 169-172, 1997
10 Pandija,S, "Achievement of high planarization efficiency in CMP of copper at a reduced down pressure" 86 (86): 367-373, 2009
1 de Jong,E.C.W, "Toward the Next Level of PCB Usage in Power Electronic Converters" 23 (23): 3151-3163, 2008
2 Fu,G, "The relationship between wafer surface pressure and wafer backside loading in Chemical Mechanical Polishing" 474 (474): 217-221, 2005
3 Seo,Y.J, "Optimization of post-CMP cleaning process for elimination of CMP slurry-induced metallic contaminations" 12 (12): 411-415, 2001
4 Venkatesh,V.C, "Observations on Polishing and Ultraprecision Machining of Semiconductor Substrate Materials" 44 (44): 611-618, 1995
5 Wolf,M.J, "Flip chip bumping technology-Status and update" 565 (565): 290-295, 2006
6 Freudenberg Mektec Europa GmbH, "Flexible Printed Circuits Open Up a Multitude of Innovative Applications"
7 Du,T, "Effect of hydrogen peroxide on oxidation of copper in CMP slurries containing glycine and Cu ions" 49 (49): 4505-4512, 2004
8 Park,S.-W, "Design of experimental optimization for ULSI CMP process applications" 66 (66): 488-495, 2003
9 Monteith,M.P, "Components of within-wafer non-uniformity in a dielectric CMP process" 169-172, 1997
10 Pandija,S, "Achievement of high planarization efficiency in CMP of copper at a reduced down pressure" 86 (86): 367-373, 2009
11 Jung-Taik Lee, "A Study on the Characteristics of a Wafer-Polishing Process according to Machining Conditions" 한국정밀공학회 10 (10): 23-28, 2009
12 Hok,G.B, "A Study of High Speed implementation for System on Chip on 2 layers Printed Circuit Board" 150-153, 2007