1 Earl fuller, "radiation characterization, and SEU mitigation of the Virtex FPGA for space based reconfigurable computing"
2 L. Adams, "handbook of radiation effects" Oxford University press 2004
3 "Xilinx Device Reliability Report, UG116 (v10.6.1)"
4 G. Allen, "Virtex-4QV static SEU characterization summary, NASA Jet Propulsion Laboratory, Xilinx" JPL Publication 2008
5 Melanine Berg, "Verification of Triple Modular Redundancy insertion for reliability & trusted systems" 2016
6 H.J. Barnaby, "Total-ionizing-dose effects in modern CMOS technologies" 53 (53): 3103-3121, 2006
7 R. C. Lacoe, "Total-dose tolerance of the Commercial Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-pm CMOS Process" 72-76, 2001
8 R.C. Lacoe, "Total dose radiation tolerance of a commercial 0.35mm CMOS process" 104-110, 1998
9 J.S. Browning, "Total dose characterization of a CMOS technology at high dose rates and temperatures" 35 (35): 1557-1562, 1988
10 J.S. Browning, "Total dose characterization of a CMOS technology at high dose rates and temperatures" 35 (35): 1988
11 Daniel Montgomery MacQueen, "Total Ionizing Dose Effects on Xilinx Field-Programmable Gate Arrays" 2000
12 "Three-dimensional Integrated Circuits"
13 D. C. Mayer, "The impact of radiationinduced failure mechanisms in electronic components on system reliability" 54 (54): 2120-2124, 2007
14 Dariusz Markowski, "The impact of radiation on electronic devices with the special consideration of neutron and gamma radiation monitoring" University of Lodz 2006
15 H. Quinn, "Terrestrial-based radiation upsets: A cautionary tale" 193-202, 2005
16 R. C. Lacoe, "TOtal-dose tolerance of the Commercial Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-mm CMOS Process, the Aerospace Corporation" Microelectronics Research Center
17 Fernanda Lima Kastensmidt, "TID in flash-based FPGA: Power Supply-Current Rise and logic function Mapping effects in Propagation-delay degradation" 58 (58): 2011
18 Stephen L. Clark, "TID and SEE Testing Results of Altera Cyclone Field Programmable Gate Array, Mathematics and Statistics Faculty Research & Creative Works" Missouri University of Science and Technology 2004
19 Xilinx, "Spartan-6 FPGA Configuration User Guide, UG380 (v2.9)"
20 H.T. Weaver, "Soft error stability of p-well versus n-well CMOS latches derived from 2D, transient simulations" 512-515, 1988
21 Kai-Chiang Wu, "Soft error rate reduction using redundancy addition and removal" 2008
22 Lucas A. Tambara, "Soft error rate in SRAMbased FPGAs under neutron-induced and TID effects" 1-6, 2014
23 H.R. Zarandi, "Soft error mitigation in switch modules of SRAM-based FPGAs" 141-144, 2007
24 M. Nicolaidis, "Soft Errors in Modern Electronic Systems, vol. 41" Springer 2011
25 M. J. Gadlage, "Single event transient pulse widths in digital microcircuits" 51 (51): 3285-3290, 2004
26 Nathaniel Anson Dodds, "Single event latchup: Hardening strategies, Triggering mechanisms, and Testing considerations" Graduate School of Vanderbilt University 2012
27 R. Koga, "Single event functional interrupt (SEFI) Sensitivity in Microcircuits" 311-318, 1997
28 Anurag Tiwari, "Saving power by mapping finite state machine into embedded memory blocks in FPGAs" 2 : 916-921, 2004
29 Cinzia Bernardeschi, "SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies" Springer Nature 30 (30): 373-390, 2015
30 Naifeng Jing, "SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms" Association for Computing Machinery (ACM) 18 (18): 1-18, 2012
31 C. Detcheverry, "SEU critical charge and sensitive area in a submicron CMOS technology" 44 (44): 2266-2273, 1997
32 Uros Legat, "SEU Recovery Mechanism for SRAM-based FPGAs" 59 (59): 2012
33 C.C. Yui, "SEU Mitigation testing of Xilinx Virtex-II FPGAs" 92-97, 2003
34 Jiri Kvasnicka, "Reliability Analysis of SRAM-based Field Programmable Gate Arrays" University in Prague 2013
35 M. Simons, "Rapid annealing in irradiated CMOS transistors" 21 (21): 172-178, 1974
36 Robert C. Baumann, "Radiationinduced soft errors in advanced semiconductor technologies" 5 (5): 305-316, 2005
37 S. Duzellier, "Radiation effects on electronic devices in space" 9 (9): 93-99, 2005
38 S.S. Rathod, "Radiation effects in MOS-based devices and Circuits: A Review" 28 (28): 451-469, 2011
39 D.M. Fleetwood, "Radiation effects at low electric fields in thermal, SIMOX, and bipolar-base oxides" 43 (43): 2537-2546, 1996
40 B. Todd, "Radiation Risks and Mitigation in electronic Systems" 245-263, 2014
41 H.T. Weaver, "RAM cell recovery mechanisms following high-energy ion strikes" 8 : 7-9, 1987
42 P.S. Winokur, "Predicting CMOS inverter response in nuclear and space environments" 30 (30): 4326-4332, 1983
43 Kai-Chiang Wu, "Power-aware soft error hardening via selective voltage scaling" 2008
44 C. E. Barnes, "Post-Irradiation Effects(PIE)in integrated circuits" 39 (39): 324-341, 1992
45 "Particle Radiation effect Mitigation Techniques in FPGAs: Synopsys application note"
46 J. A. Dennis, "Neutron flux and energy measurements" 11 (11): 1-14, 1966
47 Mattias Ohlsson, "Neutron Single Event Upsets in SRAM based FPGAs"
48 Kiran Agarwal Gupta, "Modeling of short channel MOSFET devices and analysis of design aspects for power optimisation" 3 (3): 2013
49 H. Ebrahimi, "Mitigating soft errors in SRAMbased FPGAs by decoding configuration bits in switch boxes" 42 (42): 12-20, 2011
50 ECSS, "Methods for the calculation of radiation received and its effects, and a policy for design margins, ESA-ESTEC, Standard ECSS-E-ST-10-12C"
51 C.L. Axness, "Mechanisms leading to single event upset" 33 (33): 1577-1580, 1986
52 T. P. Ma, "Ionizing Radiation effects in MOS Devices and Circuits" John wiley& Sons 1989
53 G. Barbottin, "Instabilities in Silicon Devices, New Insulators Devices and Radiation Effects, vol. 3" Elsevier 2-938, 1999
54 J. George, "Initial Single-event effects testing and mitigation in the Xilinx Virtex II-Pro FPGA" 2005
55 J.Y. Lee, "In-place decomposition for robustness in FPGA" 143-148, 2010
56 S. Srinivasan, "Improving Softerror tolerance of FPGA Configuration bits" 107-110, 2004
57 S. Jamuna, "Implementation of bistcontroller for fault detection in CLB of FPGA" 99-104, 2012
58 P.E. Dodd, "Impact of technology trends on SEU in CMOS SRAMs" 43 : 2797-2804, 1996
59 Z. Feng, "IPR: In-place reconfiguration for FPGA fault tolerance" 105-108, 2009
60 Zhe Feng, "IPF: In-Place X-filling to Mitigate Soft errors in SRAM-based FPGAs" 482-485, 2011
61 "IAEA Nuclear Energy Series No. NP-T-3.17, Application of Field Programmable Gate Arrays in Instrumentation and Control Systems of Nuclear Power Plants" International Atomic Energy Agency Vienna
62 Gregory R. Allen, "Heavy Ion Induced Single-Event Latchup Screening of Integrated Circuits Using Commercial Off-the-Shelf Evaluation Boards" 1-7, 2016
63 F. Wrobel, "Fundamentals of particle matter interaction, New challenges for radiation tolerance assemblies" 5-31, 2005
64 Christoforos N. Hadjicostis, "Finite-state machine embeddings for nonconcurrent error detection and identification" 1 (1): 2002
65 Catherine Menon and Sofia, "Field programmable gate arrays in safety-related instrumentation and control applications, Report 112" ADELARD LLP 2015
66 Felix siegle, "Fault detection, isolation and recovery schemes for space borne reconfigurable FPGA-based systems" Department of Engineering University of Leicester 2015
67 Henry Selvaraj, "FSM Implementation in embedded memory blocks of programmable logic devices using functional decomposition" 355-360, 2002
68 Ian Kuon, "FPGA architecture: survey and challenges" 2 (2): 135-253, 2007
69 J. Heiner, "FPGA PR via configuration scrubbing" 99-104, 2009
70 Maico Cassel, "Evaluating one-hot encoding finite state machines for SEU Reliability in SRAM-based FPGAs" 2006
71 Jose Rodrigo Azambuja, "Evaluating neutron Induced SEE in SRAM-based FPGA Protected by hardware-and software-based fault tolerant techniques" 60 (60): 2013
72 N. Rollins, "Evaluating TMR techniques in the presence of single event upsets" 63-, 2006
73 Prasanna Sundararajan, "Estimation of Single event upset Probability Impact of FPGA designs" MAPLD 2003
74 Anurag Tiwari, "Enhanced reliability of finite-state machines in fpga through efficient fault detection and correction" 54 (54): 2005
75 M.R. Shaneyfelt, "Effects of device scaling and geometry on MOS radiation hardness assurance" 40 (40): 1993
76 G. Messenger, "Effects of Radiation on Electronic Systems" Van Nostrand Reinhold 1992
77 Melanie Berg, "Effectiveness of internal vs. external SEU scrubbing mitigation strategies in a Xilinx FPGA: design, test, and Analysis" 1-8, 2008
78 Xilinx, "Device Reliability Report, UG116 (v10.5.1)" 2016
79 E.S.S. Reddy, "Detecting SEUcaused routing errors in SRAM-based FPGAs" 736-741, 2005
80 Fernanda Gusmao de Lima, "Designing single event upset mitigation techniques for large SRAM-based FPGA devices, vol. 11" Porto Alegre 2002
81 Fernanda Lima, "Designing Fault-Tolerant Systems into SRAM-based FPGAs" 2003
82 M. Herrera-Alzu, "Design techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers" 60 (60): 2013
83 S. Baloch, "Design of a Single event upset (SEU) Mitigation technique for programmable devices" 2006
84 C. Bolchini, "Design of VHDL-based totally self-checking finite state machine and data-path descriptions" 8 (8): 2000
85 T.S. Nidhin, "Dependable system design with soft error mitigation techniques in SRAMbased FPGAs" 2017
86 SOOS, "Csaba (European Organization for nuclear Research (CERN)), SEU effects in FPGA, how to deal with them?" 2009
87 P.E. Dodd, "Critical charge concepts for CMOS SRAMs" 42 : 1764-1771, 1995
88 Paul Graham, "Consequences and Categories of SRAM FPGA Configuration SEUs" 2003
89 Andrzej Krasniewski, "Concurrent error detection for FSMs designed for Implementation with embedded Memory blocks of FPGAs" 2007
90 Saritha P. Menon, "Computer based Core Temperature Monitoring System for Prototype Fast Breeder Reactor" Bhabha Atomic Research Centre 2013
91 M. Manghisoni, "Comparison of ionizing radiation effects in 0. 18 mm 0. 25mm CMOS technologies for analog applications" 50 (50): 1827-1833, 2003
92 K.-C. Wu, "Clock skew scheduling for soft-error-tolerant sequential circuits" 2010
93 F.B. McLean, "Charge funneling in n and p-type Si substrates" 29 : 2018-2023, 1982
94 R. C. Hughes, "Charge carrier transport phenomena in amorphous SiO2: direct measurement of mobility and carrier lifetime" 30 : 1333-, 1973
95 J. A. Zoutendyk, "Characterization of multiple-bit errors from singleion tracks in integrated circuits" 36 (36): 2267-2274, 1989
96 B. Narasimham, "Characterization of digital single event transient pulsewidths in 130nm and 90nm CMOS technologies" 54 (54): 2506-2511, 2007
97 B. Djezzar, "Channel-length Impact on Radiation-Induced threshold-voltage shift in N-MOSFET’s devices at low Gamma Rays Radiation doses" 47 (47): 2000
98 P.E. Dodd, "Basic mechanisms and modeling of single-event upset in digital microelectronics" 50 (50): 583-602, 2003
99 Nand Kumar, "Automated FSM error correction for single event upsets" 2004
100 James E. Turner, "Atoms, Radiation and Radiation Protection" Wiley 1995
101 "Assessment of equipment capability to perform reliability under severe accident conditions" IAEA TECDOC
102 J. H. Hohl, "Analytical model for single event burnout of power MOSFETs" 34 (34): 1275-1280, 1987
103 R. Rochet, "Analysis and Comparison of Fault Tolerant FSM architectures based on SEC codes" 1993
104 Gary Swift, "An experimental Survey of heavy ion induced dielectric rupture in actel Field Programmable Gate Arrays(FPGAs)" 43 (43): 967-972, 1996
105 Heather M. Quinn, "A test methodology for determining space readiness of Xilinx SRAM-based FPGA devices and designs" 58 (58): 2009
106 H. Ebrahimi, "A switch box architecture to mitigate bridging and short faults in SRAM-based FPGAs" 128-134, 2010
107 Shailesh Niranjan, "A simplified approach to fault tolerant state machine design for single event upsets" 45 (45): 1996
108 L.D. Edmonds, "A simple estimate of funneling-assisted charge collection" 38 : 828-833, 1991
109 Balkaran S. Gill, "A new Asymmetric SRAM Cell to reduce soft errors and leakage power in FPGA" 2007
110 Aiman H. El-Maleh, "A finite state machine based fault tolerance technique for sequential Circuits" 54 (54): 654-661, 2014
111 J.R. Brews, "A conceptual model of a single event gaterupture in power MOSFETs" 40 (40): 1959-1966, 1993
112 RaminRoosta, "A comparison of radiation hardened and radiation tolerant FPGAs for space applications" NASA electron. parts packaging program 2004
113 Edward Wilcox, "A Robust Strategy for Total Ionizing Dose Testing of Field Programmable Gate Arrays"
114 T.S. Nidhin, "A Review on SEU Mitigation Techniques for FPGA Configuration Memory"
115 M. Violante, "A New Hardware/Software Platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility" 54 (54): 1184-1189, 2007
116 Xilinx, "7 Series FPGAs Configuration User Guide, UG470 (v1.11)"