1 W. Lee, "Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface" 9 (9): 336-342, 2019
2 "DDR5 SDRAM Standard, JEDEC standard, JESD79-5"
3 "DDR4 SDRAM Registered DIMM Design Specification, JEDEC standard, MODULE4.20.28.B"
4 "DDR4 SDRAM Load Reduced DIMM Design Specification, JEDEC standard, MODULE4.20.27.D"
5 S. Lee, "A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces" 68 (68): 1862-1866, 2021
6 J. Seo, "A 7.8Gb/s 2.9pJ/b Single-Ended Receiver with 20 tap DFE for Highly-Reflective Channels" 28 (28): 818-822, 2020
7 S. Lee, "A 7.8 Gb/s/pin, 1.96pJ/b transceiver with phase-difference-modulation signaling for highly reflective interconnects" 67 (67): 2114-2127, 2020
8 W.-Y. Shin, "A 4.8 Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface" 494-495, 2011
9 Y.-C. Kwon, "25.4 A 20nm 6GB Function-InMemory DRAM, Based on HBM2 with a 1.2 TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications" 350-352, 2021
1 W. Lee, "Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface" 9 (9): 336-342, 2019
2 "DDR5 SDRAM Standard, JEDEC standard, JESD79-5"
3 "DDR4 SDRAM Registered DIMM Design Specification, JEDEC standard, MODULE4.20.28.B"
4 "DDR4 SDRAM Load Reduced DIMM Design Specification, JEDEC standard, MODULE4.20.27.D"
5 S. Lee, "A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces" 68 (68): 1862-1866, 2021
6 J. Seo, "A 7.8Gb/s 2.9pJ/b Single-Ended Receiver with 20 tap DFE for Highly-Reflective Channels" 28 (28): 818-822, 2020
7 S. Lee, "A 7.8 Gb/s/pin, 1.96pJ/b transceiver with phase-difference-modulation signaling for highly reflective interconnects" 67 (67): 2114-2127, 2020
8 W.-Y. Shin, "A 4.8 Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface" 494-495, 2011
9 Y.-C. Kwon, "25.4 A 20nm 6GB Function-InMemory DRAM, Based on HBM2 with a 1.2 TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications" 350-352, 2021