The Test access port and boundary-scan architecture

목차 (Table of Contents)

• CONTENTS
• Part Ⅰ Background = 1
• 1. Test Technology Prior to IEEE Std 1149.1 = 3
• 1.1 Test Technology for Loaded Boards = 3
• 1.2 Trends in Design-for-Testability = 5
• 1.3 The Effect of Miniaturization = 6
• 1.4 The Need for a New Approach = 7
• 1.5 References = 8
• 2. An Introduction to Boundary-Scan = 11
• 2.1 Scan Testing at the Board Level = 11
• 2.2 The Value of Boundary-Scan = 14
• 2.3 Testing a Board with Boundary-Scan = 15
• 2.4 Boundary-Scan for ICs That Are Not Themselves Scannable = 18
• 2.5 Boundary-Scan Compared to In-Circuit and Functional Test = 19
• 2.6 Reference = 21
• 3. The Development of IEEE Std 1149.1 = 23
• 3.1 The Joint Test Action Group = 23
• 3.2 JTAG Version 0 = 23
• 3.3 JTAG Version 1.0 = 26
• 3.4 JTAG Version 2.0 = 27
• 3.5 IEEE Std 1149.1 = 28
• 3.6 References = 29
• Part Ⅱ Tutorial = 31
• 4. IEEE Std 1149.1: The Top-Level View = 33
• 4.1 The IEEE Std 1149.1 Architecture = 33
• 4.2 The TAP = 35
• 4.3 The TAP Controller = 37
• 4.4 The Instruction Register = 43
• 4.5 The Test Data Registers = 46
• 4.6 Reference = 49
• 5. The Bypass and Device Identification Registers = 51
• 5.1 The Bypass Register = 51
• 5.2 The Device Identification Register = 52
• 5.3 Learning the Structure of an Unknown Board = 55
• 5.4 Reference = 57
• 6. The Boundary-Scan Register = 59
• 6.1 The Provision of Boundary-Scan Cells = 59
• 6.2 The Minimuin Requirement = 63
• 6.3 The INTEST Instruction = 70
• 6.4 The RUNBIST Instruction = 75
• Part Ⅲ Applications to Loaded-Board Testing = 79
• 7. Taking Advantage of Boundary-Scan = 81
• 7.1 Loaded-Board Testability Problems and Traditional Test Techniques = 81
• 7.2 100 Percent Boundary-Scan Testing = 84
• 7.3 Test-Access Strategies for Mixed -Technology Boards = 87
• 7.4 Conclusion = 94
• 7.5 References = 95
• 8. A Test Program Pseudocode = 97
• 8.1 Introduction = 97
• 8.2 Initialization = 100
• 8.3 Test Circuitry Check = 101
• 8.4 Interconnect Check = 107
• 8.5 BIST Part Check = 110
• 8.6 The Remaining Chips = 111
• 8.7 Comments on Diagnosis = 111
• 8.8 Conclusion = 112
• 8.9 Acknowledgment = 112
• 8.10 References = 112
• 9. Diagnosing Faults in the Serial Test Data Path = 115
• 9.1 Objective = 115
• 9.2 A Basic Path Test = 115
• 9.3 Use of the Device Identification Register = 116
• 9.4 More Complex Methods = 117
• 9.5 Reference = 121
• 10. In-Circuit Testing = 123
• 10.1 Mixed In-Circuit and Boundary-Scan Testing = 123
• 10.2 Method 1 = 125
• 10.3 Method 2 = 126
• 10.4 Method 3 =126
• 10.5 Conclusions = 126
• Part Ⅳ Implementation Examples and Further Applications = 127
• 11. Applications of IEEE Std 1149.1: An Overview = 129
• 11.1 Test Cost Reductions: Chip-to-System, Womb-to-Tomb = 129
• 11.2 Applications During Design and Development = 130
• 11.3 Applications During the Production Cycle = 133
• 11.4 Completing the Leverage into Field Test = 137
• 11.5 Conclusion = 139
• 11.6 Reference = 140
• 12. Benefits and Penalties of Boundary-Scan = 141
• 12.1 Benefits = 141
• 12.2 Penalties: Additional Circuitry = 143
• 12.3 Other Penalties = 146
• 12.4 Conclusion = 148
• 12.5 References = 148
• 13. Single Transport Chain = 151
• 13.1 Introduction = 151
• 13.2 The STC Architecture = 152
• 13.3 The Transport Chain = 153
• 13.4 Capture Element Design = 154
• 13.5 Update Element Design = 155
• 13.6 Transport Element Design = 155
• 13.7 A Complete STC Register Cell Design = 156
• 13.8 Conclusions = 157
• 14. Boundary-Scan Cell Provision: Some Dos and Dont's = 159
• 14.1 Clock Pins = 159
• 14.2 Logic Outside the Boundary-Scan Path = 160
• 14.3 Special Cases = 162
• 14.4 Components with Inverting Input and Output Buffers = 165
• 14.5 Complex Boundary-Scan Cells = 168
• 14.6 Conclusion = 170
• 15. Providing Boundary-Scan on Chips with Power or Output-Switching Limitations = 171
• 151 Problem Statement = 171
• 15.2 Provide More Power Pins = 173
• 15.3 Preventing Simultaneous Switching of Output Pins = 173
• 15.4 Do Not Allow Pins to be Enabled Simultaneously = 175
• 15.5 Acknowledgments = 176
• 15.6 References = 176
• 16. Tapping into ECL Chips = 177
• 16.1 The Problem = 177
• 16.2 Incorporating TTL/CMOS TAP Connections on ECL Chips = 178
• 16.3 Using a Special ECL Input Buffer for TDI, TMS, and TRST* = 179
• 16.4 Summary = 181
• 17. Cell Designs that Help Test Interconnect Shorts = 183
• 17.1 Introduction = 183
• 17.2 The Problem = 183
• 17.3 A Proposed Solution = 186
• 17.4 Conclusion = 188
• 18. Integrating Internal Scan Paths = 191
• 18.1 Problems at the Chip Level = 191
• 18.2 Problems at the Board Level = 193
• 18.3 A Solution = 194
• 18.4 Further Reading = 198
• 18.5 References = 198
• 19. Testing Mixed, Analog/Digital ICs = 199
• 19.1 The Location of the Boundary-Scan Path = 199
• 19.2 Boundary-Scan Cell Design = 200
• 19.3 Testing Analog Blocks Using Boundary-Scan = 202
• 19.4 Further Reading = 204
• 19.5 References = 204
• 20. Adding Parity and Interrupts to IEEE Std 1149.1 = 205
• 20.1 Introduction = 205
• 20.2 Why Use Parity? = 205
• 20.3 Adding Parity to Instructions = 207
• 20.4 Extending Parity to Received Test Data = 210
• 20.5 Parity Coding of Output Data = 211
• 20.6 Other Uses of TINT* = 211
• 20.7 Conclusion = 212
• 20.8 Acknowledgments = 213
• Part Ⅴ Bibliography and Reprints = 215
• 21. Bibliography = 217
• Reprints = 228
• "Chip Partitioning Aid: A Design Technique for Partitionability and Testability in VLSI" = 228
• "LOCST: A Built-In Self-Test Technique" = 234
• Reprints, continued
• "A Fast 20K Gate Array with On-Chip Test System" = 242
• "Interconnect Testing with Boundary-Scan" = 248
• "Testing and Diagnosis of Interconnects Using Boundary-Scan Architecture" = 254
• "Boundary-Scan with Built-In Self-Test" = 266
• "ASIC Testing in a Board/System Environment" = 275
• "A Universal Test and Maintenance Controller for Modules and Boards" = 279
• "The Impact of Boundary-Scan on Board Test" = 289
• "An Optimal Test Sequence for the JTAG Boundary-Scan Controller" = 302
• "A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects" = 310
• "A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects" = 318
• "A Self-Test System Architecture for Reconfigurable WSI" = 325
• "Designing and Implementing an Architecture with Boundary-Scan" = 333
• "A Language for Describing Boundary-Scan Devices" = 344
• "Functional Test and Diagnosis: A Proposed JTAG Sample Mode Scan Tester" = 357
• INDEX = 367