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    A 3 ~ 5 GHz CMOS UWB Radar Chip for Surveillance and Biometric Applications

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    https://www.riss.kr/link?id=A100429492

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    다국어 초록 (Multilingual Abstract) kakao i 다국어 번역

    A 3-5 GHz UWB radar chip in 0.13 ㎛ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.
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    A 3-5 GHz UWB radar chip in 0.13 ㎛ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the i...

    A 3-5 GHz UWB radar chip in 0.13 ㎛ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

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    목차 (Table of Contents)

    • Abstract
    • Ⅰ. INTRODUCTION
    • Ⅱ. UWB RADAR ARCHITECTURE
    • Ⅲ. CIRCUIT DESIGN
    • Ⅳ. MEASURED RESULTS
    • Abstract
    • Ⅰ. INTRODUCTION
    • Ⅱ. UWB RADAR ARCHITECTURE
    • Ⅲ. CIRCUIT DESIGN
    • Ⅳ. MEASURED RESULTS
    • Ⅴ. CONCLUSIONS
    • ACKNOWLEDGEMENTS
    • REFERENCES
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    참고문헌 (Reference)

    1 J. Borremans, "Low-area active-feedback lownoise amplifier design in scaled digital CMOS" 43 (43): 2422-2432, 2008

    2 S.M. Louwsma, "A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR" 329-332, 2007

    3 J. Choi, "A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 μm CMOS" 11 (11): 2011

    4 M. Okushima, "A DC-to-22 GHz 8.4mW compact dual-feedback wideband LNA in 90 nm digital CMOS" 295-298, 2009

    5 D. Zito, "A 90 nm CMOS SoC UWB pulse radar for respiratory rate monitoring" 40-41, 2011

    6 H. Xie, "A 52- mW 3.1-10.6-GHz Fully Integrated Correlator for IR-UWB Transceivers in 0.18 μm CMOS" 57 (57): 1546-1554, 2010

    7 T. Sato, "4-Gb/s track and hold circuit using parasitic capacitance canceller" 347-350, 2004

    1 J. Borremans, "Low-area active-feedback lownoise amplifier design in scaled digital CMOS" 43 (43): 2422-2432, 2008

    2 S.M. Louwsma, "A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR" 329-332, 2007

    3 J. Choi, "A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 μm CMOS" 11 (11): 2011

    4 M. Okushima, "A DC-to-22 GHz 8.4mW compact dual-feedback wideband LNA in 90 nm digital CMOS" 295-298, 2009

    5 D. Zito, "A 90 nm CMOS SoC UWB pulse radar for respiratory rate monitoring" 40-41, 2011

    6 H. Xie, "A 52- mW 3.1-10.6-GHz Fully Integrated Correlator for IR-UWB Transceivers in 0.18 μm CMOS" 57 (57): 1546-1554, 2010

    7 T. Sato, "4-Gb/s track and hold circuit using parasitic capacitance canceller" 347-350, 2004

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    학술지 이력

    학술지 이력
    연월일 이력구분 이력상세 등재구분
    2023 평가 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
    2020-01-01 등재 등재학술지 유지 (해외등재 학술지 평가) KCI등재
    2014-01-21 학회명변경 영문명 : The Institute Of Electronics Engineers Of Korea -> The Institute of Electronics and Information Engineers KCI등재
    2010-11-25 학술지명변경 한글명 : JOURNAL OF SEMICONDUTOR TECHNOLOGY AND SCIENCE -> JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE KCI등재
    2010-01-01 등재 등재학술지 선정 (등재후보2차) KCI등재
    2009-01-01 등재 등재후보 1차 PASS (등재후보1차) KCI등재후보
    2007-01-01 등재 등재후보학술지 선정 (신규평가) KCI등재후보
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    학술지 인용정보

    학술지 인용정보
    기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
    2016 0.42 0.13 0.35
    KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
    0.3 0.29 0.308 0.03
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