Extension of DRAM Retention Time at 77 Kelvin by Replacing Weak Rows with Large GIDL Current

다국어 초록 (Multilingual Abstract)

At 77 Kelvin, it was found that the weak cells with large gate-induced drain leakage current are quite localized in six weak rows out of the entire 524,288 rows of a 8 Gb DRAM chip. By replacing the six weak rows, the DRAM retention time was increased from 8 to 4096 seconds at 77 Kelvin.
Because this retention time is over 64,000 times longer than the JEDEC retention-time specification of 0.064 seconds, the DRAM refresh power can be reduced to a negligible level at the data center. To achieve this, the DRAM controller was modified to find weak rows by using three different data patterns at power-on reset and a reserved row of DRAM is used when access to a weak row address occurs during the normal operation.

참고문헌 (Reference)

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