Mixed hardware and software implementation is common in the design of digital systems such as communication systems, DSP applications, and embedded control systems. In general, software is easy to modify, maintain, and upgrade, though it is slow compa...
Mixed hardware and software implementation is common in the design of digital systems such as communication systems, DSP applications, and embedded control systems. In general, software is easy to modify, maintain, and upgrade, though it is slow compared to hardware. On the other hand, hardware can be made faster than software but the cost for all hardware solution is usually too high. A design issue raised in designing such systems is to find the point in between all hardware solution and all software solution to improve the performance as much as possible at a minimum hardware cost. The hardware software codesign methodology enables us to design mixed hardware and software systems with optimum performance and cost.
There are several different style of codesign, depending on what assumptions are made about the specification and the components and what elements of the system are synthesized. We introduced hardware software partitioning, which map a behavioral specification onto a hardware architecture consisting of a CPU and multiple ASICs.
In this paper, we propose a partitioning algorithm for hardware software codesign. The new algorithm exploits the urgency that resides in the system to improve the performance maximally at a minimum hardware cost with low complexity of partitioning algorithm. The key of the new algorithm is the concept of node's probability that can run in parallel with each other candidate node in both hardware software distribution graph but, it may hardly be delayed. We calculate the cost function and select the node with max value and because, we can get low cost system and satisfy the constraints with low algorithm complexity.
At present, this algorithm is incomplete. To obtain better results, it is necessary to introduce a communication model between hardware and software part, variety of Basic Scheduling Block's size, and so on.