Microprocessor handbook

목차 (Table of Contents)

• CONTENTS
• SECTION ONE INTRODUCTION TO MICROPROCESSORS = 1
• CHAPTER 1 Introduction to Microcomputers = 3
• Joseph D Greenfield, Professor of Electrical Engioeering Technology, Rochester Institute of Technology
• 1-1 INTRODUCTION = 3
• 1-2 INTRODUCTION TO THE COMPUTER = 4
• 1-3 THE MEMOFRY = 5
• 1-3.1 Memory Concepts = 5
• 1-3.2 Reading Memory = 7
• 1-3.3 Writing Memory = 7
• 1-4 SEMICONDUCTOR MEMORIES = 8
• 1-4.1 Interfacing with Memory = 8
• 1-4.2 Memory Timing = 9
• 1-4.3 Dynamic RAMs = 10
• 1-4.4 Read-Only Memories (ROMS) = 10
• 1-4.5 Programmable Read-Only Memories (PROMS) = 12
• 1-4.6 Erasable PROMs = 12
• 1-5 THEAF ARITHMETIC-LOGIC UNIT (ALU) = 12
• 1-5.1 The Condition Code -Register = 13
• 1-6 THE CONTROL SECTION = 13
• 1-6.1 Controt Unit FFs = 14
• 1-7 EXECUTION OF A SIMPLE ROUTINE = 14
• 1-7.l Sample Problem = 15
• 1-7.2 Hardware Execution of the Routine = 15
• 1-8 INTRODUCTION To PROGRAMMING = 17
• 1-8.1 Machine Language Programming = 17
• 1-8.2 Assembly Language = 18
• 1-8.3 Ftigher-Level La guages = 18
• 1-9 FLOWCHARTS = 18
• 1-9.1 Flowchart Symbols = 19
• 1-9.2 Elementary Programming = 20
• 1-10 BRANCH INSTRUCTIONS AND LOOPS = 21
• 1-10.1 Branch Instructions = 22
• 1-10.2 Decision Boxes and Conditional Branches = 23
• 1-10.3 Event Detection = 25
• 1-11 INPUT／OUTPUT = 26
• 1-11.1 Port I／O = 26
• 1-11.2 Memory-Mapped I／O = 27
• 1-11.3 Command and Status Registers = 27
• 1-12 INTERRUPTS = 28
• 1-12.1 Vectored Interrupts = 28
• 1-12.2 Maskable and Nonmaskable Interrupts = 29
• 1-13 SUMMARY = 30
• 1-14 REFERENCES = 30
• CHAPTER 2 Computer Arithmetic and Shifting = 31
• Joseph D Greenfield, Professor of Electrical Engineering Technology, Rochester Institute of Technology
• 2-1 INTRODUCTION = 31
• 2-1.1 Bits, Bytes, and Words = 33
• 2-1.2 Bytes and Nibbles = 33
• 2-2 BINARY-TO-DECIMAL CONVERSION = 34
• 2-3 DECIMAL-TO-BINARY CONVERSION = 36
• 2-4 ADDITION AND SUBTRACTION OF BINARY NUMBERS = 38
• 2-4.1 Addition of Binary Numbers = 38
• 2-4.2 Subtraction of Binary Numbers = 39
• 2-5 2s COMPLEMENT ARITHMETIC = 40
• 2-5.1 2s Complement Numbers = 41
• 2-5.2 The Range of 2s Complement Numbers = 42
• 2-5.3 Adding 2s Complement Numbers = 42
• 2-5.4 Subtraction of Binary Numbers = 43
• 2-6 LOGICAL OPERATIONS = 44
• 2-6.1 The Logical OR Operation = 44
• 2-6.2 The Logical AND Operation = 45
• 2-6.3 The EXCLUSIVE OR Operation = 45
• 2-6.4 ComplementatiOn = 45
• 2-7 HEXADECIMAL NOTATION = 46
• 2-7.1 Conversion BetWeen Hexadecimal and Binary Numbers = 46
• 2-7.2 Conversion of Hex Numbers to Decimal Numbers = 47
• 2-7.3 Hexadecimal Addition = 48
• 2-7.4 Negating Hex Numbers = 49
• 2-7.5 Octal Notation = 50
• 2-8 BRANCHING IN MICROPROCESSORS = 50
• 2-8.1 alculating Offsets = 51
• 2-8.2 Long and Short Branches = 52
• 2-9 SHIFT AND ROTATE INSTRUCTIONS = 52
• 2-9.1 Rotations = 54
• 2-10 REFERENCES = 55
• CHAPTER 3 Hardware and Software Considerations in a Microprocessor = 56
• Joseph b Greenfield, Professor of Electrical Engineering Technology, Rochester Institute of Technology
• 3-1 MACHINE, ASSEMBLY, AND HIGHER-LEVEL LANGUAGES = 56
• 3-1.1 Machine Language = 56
• 3-1.2 Assembiy Language Programming = 58
• 3-1.3 High7LevelLanguages = 62
• 3-2 INSTRUCTION MODES = 63
• 3-2.1 Inherent or Implied Instructions = 63
• 3-2.2 Immediate Instructions = 63
• 3-2.3 Direct Instructions = 64
• 3-2.4 Indexed Instructions = 64
• 3-2.5 Indirect Addressing = 65
• 3-2.6 Relative Instructions = 65
• 3-3 REGISTERS AND ACCUMULATORS = 66
• 3-3.1 The 8080／8085 Registers and Accumulator = 66
• 3-3.2 The 6800, 6809, and 6502 Registers = 66
• 3-4 SUBROUTINES AND STACKS = 67
• 3-4.1 Subroutines = 67
• 3-4.2 Stacks = 68
• 3-4.3 The Stack Pointer = 69
• 3-4.4 PUSHes and PULLs or POPs = 69
• 3-4.5 Stacks in Newer Microprocessors = 70
• 3-5 INTERRUPTS = 70
• 3-5.1 Level- and Edge-Sensitive Interrupts = 71
• 3-5.2 Maskable Interrupts = 71
• 3-5.3 Nonmaskabie Interrupts (NMI) = 72
• 3-5.4 Interrupts on the 8080 and 8085 = 73
• 3-5.5 Interrupts on the 6800 = 73
• 3-6 MICROPROCESSOR BUSES = 74
• 3-6.1 The Data Bus = 74
• 3-6.2 The Address Bus = 75
• 3-6.3 The Control Bus = 75
• 3-6.4 Multiplexed Buses = 76
• 3-6.5 Direct Memory Access = 76
• 3-7 REFERENCES = 77
• SECTION TWO EIGHT-BIT MICROPROCESSORS = 79
• CHAPTER 4 The Intel 8080 = 81
• Walter Foley, Eastman Kodak Corp
• 4-1 Architecture = 81
• 4-1.1 Registers = 81
• 4-1.2 The Accumulator = 83
• 4-1.3 The Flags = 83
• 4-1.4 Stack = 84
• 4-2 ADDRESSING MODES = 84
• 4-2.1 Implied Addressing = 85
• 4-2.2 Register Addressing = 85
• 4-2.3 Immediate Addressing = 85
• 4-2.4 Direct Addressing = 85
• 4-2.5 Register Indirect Addressing = 86
• 4-3 INSTRUCTION FORMAT = 86
• 4-4 INSTRUCTION SET = 86
• 4-4.1 The Data Transfer Group = 87
• 4-4.2 The Arithmetic Group = 93
• 4-4.3 The Logical Group = 104
• 4-4.4 The Branch Group = 107
• 4-4.5 Stack, I／O, and Machine Control = 110
• 4-5 THE CPU = 112
• 4-5.1 Clock Generation = 115
• 475.2 Machine Cycles and T States = 115
• 4-5.3 Status Byte Decoding = 121
• 4-5.4 Instruction Timing = 123
• 4-5.5 System Control Devices = 124
• 4-5.6 RESET Signal = 125
• 4-6 MEMORY INTERFACE = 126
• 4-7 REFERENCES = 127
• CHAPTER 5 The Intel 8085 = 142
• Walter Foley, Eastman Kodak Corp
• 5-1 ARCHITECTURE = 142
• 5-1.1 The 8085 Oscillator Circuit = 143
• 5-1.2 The Multiplexed Data Bus = 143
• 5-1.3 Other 8085 Lines = 146
• 5-2 INPUT AND OUTPUT PORTS = 146
• 5-2.1 IN and OUT Timing = 148
• 5-2.2 Execution of the OUT Instruction = 148
• 5-2.3 Execution of the IN Instruction = 149
• 5-2.4 SID and SOD = 150
• 5-3 INTERRUPTS ON THE 8080 AND 8085 = 150
• 5-3.1 The RESTART Instruction = 150
• 5-3.2 New 8085 Interrupt Vectors = 152
• 5-3.3 The CALL Instruction = 153
• 5-4 INSTRUCTION SET = 156
• 5-4.1 The Interrupt Mask Register = 156
• 5-4.2 Sim = 156
• 5-4.3 RIM = 158
• 5-4.4 Other Instructions = 159
• 5-5 THE CPU = 161
• 5-5.1 Status Information Decoding = 163
• 5-5.2 Demultiplexing Address and Data = 163
• 5-5.3 Wait States = 164
• 5-6 SPECIAL PERIPHERAL DEVICES = 165
• 5-6.1 The 8255 = 168
• 5-6.2 Strobed Input Mode = 171
• 5-6.3 Strobed output Mode = 173
• 5-6.4 Mode 2 Operation = 176
• 5-6.5 The Status Word = 177
• 5-6.6 A Data Communications Controller Using the 8255 = 178
• 5-7 REFERENCES = 183
• CHAPTER 6 The Zilog Z80 = 184
• Glenn A Barlis, Mobil Chemical Co
• 6-1 INTRODUCTION = 184
• 6-2 ARCHITECTURE = 185
• 6-3 ADDRESSING MODES = 189
• 6-3.1 Immediate Addressing = 189
• 6-3.2 immediate Extended Addressing = 199
• 6-3.3 Modified Page Zero Addressing = 200
• 6-3.4 Register Addressing = 200
• 6-3.5 Implied Addressing = 200
• 6-3.6 Register Indirect Addressing = 201
• 6-3.7 Stack Addressing = 201
• 6-3.8 Extended Addressing = 201
• 6-3.9 Relative Addressing = 202
• 6-3.10 Indexed Addressing = 203
• 6-3.11 Bit Addressing = 203
• 6-4 INSTRUCTION SET = 204
• 6-4.1 8-Bit Load Group = 204
• 6-4.2 16-Bit Load Group = 206
• 6-4.3 Exchange Group = 207
• 6-4.4 Block Transfer Group = 208
• 6-4.5 Block Search Group = 210
• 6-4.6 8-Bit Arithmetic and Logic Group = 212
• 6-4.7 General-Purpose AF Group = 213
• 6-4.8 Miscellaneous CPU Control Group = 213
• 6-4.9 16-Bit Arithmetic Group = 214
• 6-4.10 ROTATE and SHIFT Group = 216
• 6-4.11 Bit Manipulation Group = 220
• 6-4.12 JUMP Group = 221
• 6-4.13 CALL and RETURN Group = 224
• 6-4.14 RESTART Group = 224
• 6-4.15 Input Group = 224
• 6-4.16 Output Group = 227
• 6-5 CPU PIN OUT AND DESCRIPTION = 227
• 6-6 I／O PROCESSING AND INTERRUPTS = 229
• 6-6.1 WAIT and BUS Requests = 230
• 6-6.2 Nonmaskable Interrupts = 230
• 6-6.3 Maskable Interrupts = 231
• 6-7 SAMPLE APPLICATION = 233
• 6-7.1 Z80 CPU = 233
• 6-7.2 Clock Circuit = 233
• 6-7.3 RESET Circuit = 236
• 6-7.4 READ／WRITE Encoding = 236
• 6-7.5 Memory = 236
• 6-7.6 Memory Address Selection = 236
• 6-7.7 I／O Port Address Decoding = 236
• 6-7.8 Counter／Timer Circuit = 237
• 6-7.9 Parallel Interface Controller = 238
• 6-7.10 Serial I／O Circuit = 238
• 6-7.11 Program Listing = 239
• 6-8 REFERENCES = 252
• CHAPTER 7 The Motorola 6800 = 253
• Joseph D Greenfield, Professor of Electrical Engineering, Rochester Institute of Technology
• 7-1 INTRODUCTION = 253
• 7-2 THE 68M REGISTERS AND ACCUMULATORS = 253
• 7-2.1 The 8-Bit Registers = 253
• 7-2.2 The 16-Bit Registers = 254
• 7-3 6800 Addressing Modes = 254
• 7-3.1 Immediate Addressing Instructions = 257
• 7-3.2 Direct Instructions = 257
• 7-3.3 Extended Instructions = 258
• 7-3.4 Indexed Instructions = 259
• 7-3.5 Implied Addressing = 269
• 7-3.6 Relative Instructions = 260
• 7-4 CONDITION CODES = 260
• 7-4.1 The Z Bit = 260
• 7-4.2 The C Bit = 261
• 7-4.3 The N Bit = 261
• 7-4.4 The V Bit = 261
• 7-4.6 Manipulations of the Condition Code Register = 263
• 7-5 BCD ADDITION AND THE H BIT = 263
• 7-5.1 Adding BCD Nubers = 263
• 7-5.2 the DAA lnstructioit = 264
• 7-6 LOGIC INSTRUCTIONS = 266
• 7-6.1 Setting and Clearing Specific Bits = 266
• 7-6.2 Testing Bits = 266
• 7-6.3 Compare Instructions = 266
• 7-6.4 The TEST Instruction = 267
• 7-7 OTHER 6800 INSTRUCTIONS = 267
• 7-7.1 CLEAR, INCREMENT, and DECREMENT Instructions = 267
• 7-7.2 SHIFT and ROTATE Instructions = 267
• 7-7.3 Accumulator Transfer, Instruction = 268
• 7-7.4 COMPLEMENT and NEGATE Instructions = 268
• 7-8 BRANCH AND JUMP INSTRUCTIONS = 268
• 7-8.1 JUMP Instructions = 268
• 7-8.2 Unconditional-BRANCH Instructions = 269
• 7-8.3 Out-of-Range BRANCHes = 270
• 7-8.4 Conditional BRANCH, Instructions = 270
• 7-8.5 Other Conditional BRANCH Instructions = 272
• 7-9 STACKS = 274
• 7-9.1 The Stack Pointer = 274
• 7-9.2 PUSH and PULL = 275
• 7-10 SUBROUTINES = 275
• 7-10.1 JUMPS to Subroutines = 277
• 7-10.2 RETURNI FR M SUBROUTINE = 277
• 7-10.3 Nested Subroutines = 278
• 7-10.4 Use of Registers During Subroutines = 279
• 7-11 THE 6800 SIGNAL LINES = 280
• 7-11.1 READ／WRITE (R／W) = 280
• 7-11.2 Valid MEMORY Address (VMA) = 290
• 7-11.3 Data Bus Enable (DBE) = 282
• 7-11.4 Interrupt Request, Nonmaskable Interrupt, and RESET = 282
• 7-11.5 Phase 1 (Φ1) and Phase 2 (Φ2) of the Clock = 282
• 7-11.6 Halt and Run Modes = 282
• 7-11.7 Bus Available (BA) = 282
• 7-11.8 Tri-State Control (TSC) = 282
• 7-12 CLOCK OPERATION = 283
• 7-12.1 Instruction Bytes and Clock Cycles = 283
• 7-13 INTRODUCTION TO INTERRUPTS = 285
• 7-13.1 Vectored Interrupts = 286
• 7-13.2 Reset (RST) = 287
• 7-13.3 The IRO Interrupt = 287
• 7-13.4 Nested Interrupts = 289
• 7-13.5 Return from Interrupt (RTI) = 289
• 7-13.6 Nonmaskable Interrupt = 289
• 7-13.7 The Software Interrupt (SWI) = 290
• 7-13.8 The WAI Instruction = 290
• 7-14 INPUT／OUTPUT = 290
• 7-14.1 The PIA Registers = 290
• 7-14.2 The PIA／6800 Interface = 291
• 7-14.3 The Interface Between the PIA and External Devices = 292
• 7-14.4 Data Transfers Between the PIA and External Devices = 292
• 7-14.5 The Direction Register = 293
• 7-14.6 The Data Register = 294
• 7-14.7 Initializing the PIA = 294
• 7-15 HANDSHAKING WITH THE PIA = 296
• 7-15.1 Control Lines CAl and CB1 = 296
• 7-15.2 Control Lines CA2 and CB2 = 300
• 7-15.3 UseDf CB2 as an Output in the Handshake Mode = 300
• 7-16.4 Use of C82 in the Pulse Mode = 304
• 7-15.5 ON-OFF Control of CP2 = 305
• 7-15.6 Control of CA2 as an Output (Handshaking Mode) = 305
• 7-15.7 Pulse Mode for CA2 = 307
• 7-15.8 ON-OFF Mode for CA2 = 307
• 7-16 REFERENCES = 307
• CHAPTER 8 THE MC6809 = 308
• Tim Ahrens, Motorola
• 8-1 ARCHITECTURE OF THE MC6809 = 308
• 8-1.1 Accumulators = 308
• 8-1.2 lridexregisters = 309
• 8-1.3 Stack Pointers (S, U) = 309
• 8-1.4 Direct Page Register (DP) = 309
• 8-1.5 Conditi n Code Register (CC) = 310
• 8-1.6 Program Counter (PC) = 312
• 8-2 MODES OF INSTRUCTION EXECUTION (ADDRESSING MODES) = 312
• 8-2.1 Inherent = 313
• 8-2.2 Immediate Addressing = 313
• 8-2.3 Extended Addressing = 313
• 8-2.4 Extended Indirect = 313
• 8-2.5 Direct Addressing = 314
• 8-2.6 Register Addressing = 314
• 8-3 INDEXED ADDRESSING = 314
• 8-3.1 Zero-Offset Indexed = 317
• 8-3.2 Constant-Offset Indexed = 317
• 8-3.3 Adcumulator-Offset Indexed = 318
• 8-3.4 Auto Increment／Decrement Indexed = 318
• 8-3.5 Indexed Indirect = 319
• 8-3.6 Relative Addressing = 320
• 8-3.7 Program Counter Relative = 320
• 8-4 M6809 INSTRUCTION SET = 320
• 8-4.1 PSHU／PSHS = 321
• 8-4.2 PULU／PULS = 321
• 8-4.3 TFR／EXG = 322
• 8-4.4 LEAX／LEAY／LEAU／LEAS = 322
• 8-4.5 MUL = 324
• 8-5 LONG AND SHORT RELATIVE BRANCHES = 324
• 8-6 SYNC = 324
• 8-7 SOFTWARE INTERRUPTS = 324
• 8-8 16-BIT OPERATION = 325
• 8-9 PIN OUT AND SIGNAL DESCRIPTIONS = 325
• 8-9.1 Power (Vss, Vcc) = 325
• 8-9.2 XTAL, EXTAL = 329
• 8-9.3 E, Q = 329
• 8-9.4 Address Bus (AO-Al5) = 329
• 8-9.5 Data Bus (DO-D7) = 329
• 8-9.6 READ／WRITE (R／W) = 329
• 8-9.7 RESET = 330
• 8-9.8 HALT = 330
• 8-9.9 Bus Available, Bus Status (13A, BS) = 330
• 8-9.10 INTERRUPT ACKNOWLEDGE = 331
• 8-9.11 NONMASKABLE INTERRUPT (NMI) = 331
• 8-9.12 FAST INTERRUPT REQUEST (FIBO) = 332
• 8-9.13 INTERRUPT REQUEST = 332
• 8-9.14 MRDY = 332
• 8-9.15 DMA／BREQ = 332
• 8-10 PINS IMPLEMENTED-ONLY ON THE MC6809E = 333
• 8-10.1 Clock Inputs E, Q = 333
• 8-10.2 BUSY = 333
• 8-10.3 AVMA = 334
• 8-10.4 LIC = 334
• 8-10.5 TSC = 335
• 8-11 MPU OPERATION = 335
• 8-12 THE MCGO09 EVALUATION BOARD = 335
• 8-13 CONVERSION CONSIDERATIONS = 346
• 8-14 SUMMARY = 346
• 8-15 REFERENCES = 346
• CHAPTER 9 The 6500 Family of Microprocessors = 347
• Marvin L De Jong, Department of Mathematics-Physics The School of the Ozarks
• 9-1 INTRODUCTION = 347
• 9-2 A PROGRAMMER'S MODEL OF THE 6500 ARCHITECTURE = 348
• 9-3 THE 6600 FAMILY INSTRUCTION SET = 353
• 9-4 BRANCHES, JUMPS, AND SUBROUTINE CALLS = 358
• 9-5 INTERRUPTS = 360
• 9-6 ADDRESSING MODES = 362
• 9-7 THE 6502 SIGNALS = 364
• 9-8 6502 SYSTEM TIMING = 369
• 9-9 INPUT／OUTPUT = 372
• 9-10 APPLICATIONS = 376
• 9-11 REFERENCES = 383
• SECTION THREE SIXTEEN-BIT MICROPROCESSORS = 385
• CHAPTER 10 Intel 8086 and 8088 Microprocessors = 347
• Windsor Thomas, Professor of Electrical Engineering Technology, State University of New York
• 10-1 INTRODUCTION = 387
• 10-2 8086 ARCHITECTURE = 387
• 10-3 8086 REGISTERS = 388
• 10-3.1 General Registers = 388
• 10-3.2 Segment Registers = 389
• 10-3.3 Instruction Pointer = 390
• 10-3.4 Status Register = 391
• 10-4 COMPARISON OF THE 8086 AND 8080／8085 ARCHITECTURE = 392
• 10-5 THE STACK = 393
• 10-6 SYSTEM RESET = 393
• 10-7 ADDRESSING MODES = 393
• 10-7.1 Register Addressing = 394
• 10-7.2 Immediate Addressing = 394
• 10-7.3 Effective-Address Calculation = 394
• 10-7.4 Direct Addressing = 394
• 10-7.5 Register Indirect Addressing = 394
• 10-7.6 Based Addressing = 395
• 10-7.7 Indexed Addressing = 395
• 10-7.8 Based Indexed Addressing = 395
• 10-7.9 String Addressing = 395
• 10-7.10 I／O Port Addressing = 395
• 10-8 8086 INSTRUCTION SET = 395
• 10-8.1 Data Transfer Instiluctjgn = 396
• 10-8.2 Arithmetic and Logical Instructions = 397
• 10-8.3 String Instructions = 397
• 10-8.4 Program Transfer Instruction = 400
• 10-8.5 Processor Control Instructions = 402
• 10-9 8066／8088 PINS AND MODE SELECTION = 403
• 10-9.1 8086／Pin Out = 403
• 10-9.2 Mode Selection = 408
• 10-10 INTERRUPT CAPABILITIES = 408
• 10-11 COPROCESSORS = 410
• 10-11.1 The 8089 Input／Output Processor = 410
• 10-11.2 Functional Description = 411
• 10-11.3 I／O Coprocessor Operation = 416
• 10-11.4 Initialization = 417
• 10-11.5 Numeric Data Processor = 426
• 10-12 REFERENCES = 441
• CHAPTER 11 The ZBOOO 16-BIT Microprocessors = 442
• Steve Sharp, American Microsystems, Inc = 442
• 11-1 INTRODUCTION = 442
• 11-2 GENERAL ARCHITECTURE = 443
• 11-2.1 General-Purpose Register Set = 444
• 11-2.2 Instruction Set = 448
• 11-2.3 Data Types = 447
• 11-2.4 Addressing Modes = 448
• 11-2.5 Memory Address Spaces = 450
• 11-2.6 System／Norrrval odes of Operation = 451
• 11-2.7 Separate I／O Address Spaces = 452
• 11-2.8 Interrupt Structure = 452
• 11-2.9 Multiprocessing = 453
• 11-2.10 Large Address Space for Z8001 and Z8003 = 453
• 11-2.11 Segmented Address for Z8001 and Z8003 = 453
• 11-3 THE Z800 FAMILY OF CPUS = 454
• 11-3.1 Z8002 Nonsegmented CPU = 454
• 11-3.2 Z8001 Segmented CPU = 454
• 11-3.3 Z8003 Virtual Memory CPU = 455
• 11-4 INSTRUCTION SET = 455
• 11-4.1 Load and Exchange = 455
• 11-4.2 Arithmetic = 456
• 11-4.3 Logical = 456
• 11-4.4 Program Control = 457
• 11-4.4 Bit Manipulation = 457
• 11-4.6 Rotate and Shift = 457
• 11-4.7 Block Transfer-and String Manipulation = 458
• 11-4.8 Input／OUtput = 459
• 11-4.9 CPU Control = 459
• 11-4.10 Extended Instructions = 460
• 11-5 HARDWARE INTERFACE = 460
• 11-5.1 Multiplexed Bus (Z-Bus) = 460
• 11-5.2 Address Strobe and Data Strobe = 460
• 11-5.3 Input／Output Operation = 461
• 11-5.4 Interrupts and Traps = 462
• 11-5.5 Bus Request and Acknowledge = 462
• 11-6 CPU SUPPORT DEVICES = 462
• 11-6.1 Z8010 MMU = 463
• 11-6.2 Z8016 DTC = 463
• 11-6.3 Z8070 APU = 463
• 11-7 OFTWARE INTERFACE = 464
• 11-7.1 Context Switching = 464
• 11-7.2 Interrupts = 464
• 11-7.3 System Call Instruction = 465
• 11-7.4 Segment Trap and Abort = 465
• 11-8 REFERENCES = 466
• CHAPTER 12 THE MOTOROLA 68000 = 475
• Dennis Pfleger, Motorola Microsystem
• 12-1 PRIMARY FEATURES = 475
• 12-2 THE SOFTWARE DESIGNER'S VIEW OF THE MC68000 = 478
• 12-2.1 Data Registers = 479
• 12-2.2 Address Registers = 479
• 12-2.3 Status Registers = 479
• 12-3 ADDRESSING TYPES = 480
• 12-3.1 Assemblers = 495
• 12-4 SPECIAL INSTRUCTIONS = 495
• 12-5 STACKS AND PROCEDURE CALLS = 496
• 12-6 TRAPS AND ERROR RECOVERY = 499
• 12-6.1 User and Supervisory States = 409
• 12-7 INTERRUPTS AND I／O = 501
• 12-7.1 Memory-mapped I／O = 501
• 12-7.2 Interlocks = 501
• 12-8 DATA ORGANIZATION = 561
• 12-9 THE HARDWARE DESIGNER'S VIEW OF THE MC68000 = 505
• 12-9.1 The Address Bus = 505
• 12-9.2 The Data Bus = 506
• 12-9.3 System Control = 506
• 12-9.4 Systems Control = 507
• 12-10 THE DATA SFFEFT AND USER'S GUIDE = 508
• 12-10.1 Timing = 508
• 12-10.2 The Programmer's Reference Manual = 511
• 12-11 THE Md6845l MEMORY MANAGEMENT UN = 512
• 12-12 REFERENCES = 513
• SECTION FOUR PERIPHERAL ICs = 515
• CHAPTER 13 Intel Peripheral Circuits
• Windsor Thomas, Professor of Electrical Engineering Technology, State University of New York
• 13-1 INTRODUCTION = 517
• 13-2 8251A USART = 517
• 13-2.1 Functional Description = 517
• 13-2.2 Major Functional Blocks and Pins = 519
• 13-2.3 Device Pins = 520
• 13-2.4 General Operation = 523
• 13-2.5 Asynchronous Mode = 525
• 13-2.6 Synchronous Mode = 526
• 13-2.7 Command Instructions = 526
• 13-2.8 Status Register = 528
• 13-2.9 Design Considerations = 529
• 13-3 8253 PROGRAMMABLE TIMER／COUNTER = 530
• 13-3.1 Functional Description = 530
• 13-3.2 Device Pins = 530
• 13-3.3 Principles of Operation = 533
• 13-3.4 Counter Initialization = 533
• 13-3.5 Modes of Operation = 535
• 13-3.6 Reading the Counter = 538
• 13-4 827S PROGRAMMABLE CRT CONTROLLER = 540
• 13-4.1 Functional Description = 540
• 13-4.2 Device Pins = 542
• 13-4.3 General Operation = 544
• 13-4.4 Display Format = 545
• 13-4.5 Device Initialization = 547
• 13-5 THE 8279 PROGRAMMABLE KEYBOARD／DISPLAY INTERFACE = 551
• 13-5.1 Functional Description = 551
• 13-5.2 Device Pins = 555
• 13-5.3 Device Operation = 556
• 13-6 REFERENCES = 558
• CHAPTER 14 Motorola Peripherals = 559
• Joseph D Greenfield, Professor of Electrical Engineering, Rochester Institute of Technology,and Tom Hardy, Motorola
• 14-1 THE 6840 PROGRAMMABLE TIMER MODULE = 559
• 14-1.1 The Hardware Interface to the 6840 = 560
• 14-1.2 GenerW System Operation = 561
• 14-1.3 Programming the Control Registers = 563
• 14-1.4 Resets = 564
• 14-1.5 Counter Initialization = 564
• 14-1.6 16-Bit and Dual 8-Bit ModeS = 564
• 14-1.7 Single-Shot Mode = 567
• 14-2 SERIAL DATA TRANSMISSION = 568
• 14-2.1 Asynchronous Transmission = 570
• 14-2.2 Synchronous Communications = 571
• 14-3 THE ACIA = 572
• 14-3.1 Parallel-to-Serial and Serial-to-Parallel Conversion = 573
• 14-3.2 ACIA Registers = 574
• 14-3.3 ACIA Signal Lines = 575
• 14-3.4 The ACIA Control Register = 575
• 14-3.5 ACFA POWER-ON RESET = 580
• 14-3.6 The ACIA Status Register = 580
• 14-3.7 Uses of the ACIA = 583
• 14-4 HIGH-SPEED SERIAL COMMUNICATION WITH THE MC6854 ADVANSED DATA LINK CONTROLLER = 584
• 14-4.1 The Fields Within a Frame = 588
• 14-4.2 Abort G6nditi6ns = 587
• 14-4.3 FIFOs = 587
• 14-4.4 Loop Transmission = 589
• 14-4.5 MC6854 ADLC Hardware = 591
• 14-4.6 MC6854 Used with DMA = 592
• 14-4.7 Internal Registers in the MC6854 = 594
• 14-4.8 The MC6852 Synchronous Serial Data Adapter (SSDA) = 595
• 14-5 THE MC6845 CRTC = 595
• 14-5.1 The MC6845 Signals = 598
• 14-5.2 The MC6845 Registers = 601
• 14-5.3 Setting Up a CRTC System = 604
• 14-5.4 An Example of a CRTC Design = 606
• 14-6 REFERENCES = 610
• PAPTER 15 Zilog Perloberals = 611
• Steve Sharp, American MicrosysteMS, Inc
• 15-1 OVEAVIEW = 611
• 15-2 HARDWARE INTERFACE = 612
• 15-2 1 The Z-Bus Series of Peripherals = 612
• l5-2 2 Signal Lines = 612
• 15-2 3 Nonmultiplexed Bus Peripherals = 614
• 15-3 INTERRUPT STRUCTURE = 614
• 15-4 Z8036 Z-CIO = 617
• 15-5 z8030 Z-SCC = 620
• 15-6 Z8038 Z-FIO = 624
• 15-7 FIFO BUFFER EXPANSION = 626
• 15-8 Z8065 Z-BEP = 627
• 15-9 Z8068 Z-DCP = 628
• 15-10 ZSO-FAMILY PERIPHERALS = 629
• 15-10.1 Interface = 629
• 15-11 Z80 PIO = 630
• 15-12 Z80 CTC = 630
• 15-13 ZSO SIO = 630
• 15-14 REFERENCES = 632
• INDEX = 633
• INDEX OF INTEGRATED CIRCUITS = 635