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      진공에서 소성 가능한 프릿을 이용한 평판디스플레이 진공실장기술 = Vacuum Sealing Technology of the Flat Panel Display by using the Frit Glass Heatable in Vacuum

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      https://www.riss.kr/link?id=A101837363

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      다국어 초록 (Multilingual Abstract) kakao i 다국어 번역

      One of the important issues for fabricating the microelectronic display devices such as FED, PDP, and VFD is to obtain a high vacuum level inside the panel. In addition, sustaining the initial high vacuum level permanently is also very important. In the conventional packing technology using a tabulation method, it is not possible to obtain a satisfiable vacuum level for a proper operation. In case of FED, the poor vacuum level results in the increase of operating voltage for electron emission from field emitter tips and an arcing problem, resultantly shortening a life time. Furthermore, the reduction of a sealing process time in the PDP production is very important in respect of commercial product. The most probable method for obtaining the initial high vacuum level inside the space with such a miniature and complex geometry is a vacuum in-line sealing which seals two glass plates within a high vacuum chamber. The critical solution for the vacuum sealing is to develop a frit glass to avoid the bubbling or crack problems during the sealing process at high temperature of about $400^{\circ}C$ under the vacuum environment. In this study, the suitable frit power was developed using a mixture of vitreous and crystalline type frit powders, and a vacuum sealed CNT FED with 2 inch diagonal size was fabricated and successfully operated.
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      One of the important issues for fabricating the microelectronic display devices such as FED, PDP, and VFD is to obtain a high vacuum level inside the panel. In addition, sustaining the initial high vacuum level permanently is also very important. In t...

      One of the important issues for fabricating the microelectronic display devices such as FED, PDP, and VFD is to obtain a high vacuum level inside the panel. In addition, sustaining the initial high vacuum level permanently is also very important. In the conventional packing technology using a tabulation method, it is not possible to obtain a satisfiable vacuum level for a proper operation. In case of FED, the poor vacuum level results in the increase of operating voltage for electron emission from field emitter tips and an arcing problem, resultantly shortening a life time. Furthermore, the reduction of a sealing process time in the PDP production is very important in respect of commercial product. The most probable method for obtaining the initial high vacuum level inside the space with such a miniature and complex geometry is a vacuum in-line sealing which seals two glass plates within a high vacuum chamber. The critical solution for the vacuum sealing is to develop a frit glass to avoid the bubbling or crack problems during the sealing process at high temperature of about $400^{\circ}C$ under the vacuum environment. In this study, the suitable frit power was developed using a mixture of vitreous and crystalline type frit powders, and a vacuum sealed CNT FED with 2 inch diagonal size was fabricated and successfully operated.

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      참고문헌 (Reference)

      1 J. A. Castellano, 41 : 67-, 1998

      2 B. R. Chalamala, 35 : 42-, 1998

      3 T. Yano, 55 : 125-, 2012

      4 C. W. Oh, 16 : 807-, 1998

      5 D. J. Lee, 74 : 105-, 2004

      6 C. Boffito, 35 : 212-, 1986

      7 Roth A., "Vacuum technology" 329-, 1978

      1 J. A. Castellano, 41 : 67-, 1998

      2 B. R. Chalamala, 35 : 42-, 1998

      3 T. Yano, 55 : 125-, 2012

      4 C. W. Oh, 16 : 807-, 1998

      5 D. J. Lee, 74 : 105-, 2004

      6 C. Boffito, 35 : 212-, 1986

      7 Roth A., "Vacuum technology" 329-, 1978

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2026 평가예정 재인증평가 신청대상 (재인증)
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      2013-01-01 평가 등재 1차 FAIL (등재유지) KCI등재
      2010-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2008-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2006-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2005-05-30 학회명변경 영문명 : 미등록 -> The Korean Institute of Electrical and Electronic Material Engineers KCI등재
      2004-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2001-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      1998-07-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.13 0.13 0.13
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.14 0.14 0.247 0.06
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