클록 보정회로를 가진 1V 1.6-GS/s 6-bit Flash ADC = 1V 1.6-GS/s 6-bit Flash ADC with Clock Calibration Circuit

다국어 초록 (Multilingual Abstract)

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

참고문헌 (Reference)

1 Y.-C. Jang, "An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator" E90-C (E90-C): 1156-1164, 2007

2 H. Banba, "A CMOS Bandgap Reference Circuit with Sub-1-V Operation" 34 (34): 670-674, 1999

3 G. Geelen, "A 6-bit 1.1 Gsample/s CMOS A/D converter" 128-129, 2001

4 P. C. S. Scholtens, "A 6-b1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination" 37 (37): 1599-1609, 2002

5 M. Choi, "A 6-b 1.3Gsample/s A/D converter in 0.35-μm CMOS" 36 (36): 1847-1858, 2001

6 T.B. Cho, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter" 30 (30): 166-172, 1995

7 장영찬, "A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration" 대한전자공학회 8 (8): 318-325, 2008

8 S.-H. Kim, "1V 2.56-GS/s6-bit Flash ADC with Clock Calibration Circuit" 436-439, 2011