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이 학술지의 논문 검색
Transistor Reordering Rules for Power Reduction in CMOS Gates
Shen, W.-Z.; Lin, J.-Y.; Wang, F.-W. IEEE 1995 p.1-6
Power Reduction by Gate Sizing with Path-Oriented Slack Calculation
Lin, H.-R.; Ting Ting Hwang IEEE 1995 p.7-12
Auriga2: A 4.7 Million-Transistor CISC Microprocessor
Tual, J. P.; Thill, M.; Bernard, C.; Nguyen, H. N. IEEE 1995 p.19-26
Automatic Design for Bit-Serial Memory Sharing Processor Array Architecture
Kunieda, H.; Liao, Y.; Li, D.; Ito, K. IEEE 1995 p.27-32
Stoht - An SDL-to-Hardware Translator
Bonatti, I. S.; Figueiredo, R. J. O. IEEE 1995 p.33-36
Enhancing a VHDL Based Design Methodology with Application Specific Data Abstraction
Lindqvist, L. IEEE 1995 p.37-39
Design Automation 2000-Challenges for the Gigabit Era
Wallace, R. K.; Yoshida, K.; Costello, J. B.; Edson, J. H. IEEE 1995 p.41-42
A Scheduling Algorithm for Synthesis of Bus-Partitioned Architectures
Moshnyaga, V. G.; Ohbayashi, F.; Tamaru, K. IEEE 1995 p.43-48