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      시정수 비교기를 이용한 작은 크기의 위상고정루프 = Small-size PLL with time constant comparator

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      https://www.riss.kr/link?id=A105192085

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      다국어 초록 (Multilingual Abstract) kakao i 다국어 번역

      A novel structure of phase locked loop (PLL) with a time constant comparator and a current compensator has been proposed. The proposed PLL uses small capacitors which are impossible for stable operation in a conventional PLL. It is small enough to be integrated into a single chip. The time constant comparator detects the loop filter output voltage variations using signals which are passed through small and large RC time constants. The signal from the large RC time constant node is the average of the loop filter output voltage. The output voltage of another node is approximately equal to the present loop filter voltage. The output of the time constant comparator controls a current compensator and charge/discharge small size loop filter capacitors. It makes the proposed PLL operate stably. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.
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      A novel structure of phase locked loop (PLL) with a time constant comparator and a current compensator has been proposed. The proposed PLL uses small capacitors which are impossible for stable operation in a conventional PLL. It is small enough to be ...

      A novel structure of phase locked loop (PLL) with a time constant comparator and a current compensator has been proposed. The proposed PLL uses small capacitors which are impossible for stable operation in a conventional PLL. It is small enough to be integrated into a single chip. The time constant comparator detects the loop filter output voltage variations using signals which are passed through small and large RC time constants. The signal from the large RC time constant node is the average of the loop filter output voltage. The output voltage of another node is approximately equal to the present loop filter voltage. The output of the time constant comparator controls a current compensator and charge/discharge small size loop filter capacitors. It makes the proposed PLL operate stably. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

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      참고문헌 (Reference)

      1 안성진, "전하펌프를 이용한 루프 필터 전압변화 보상 위상고정루프" 한국정보통신학회 20 (20): 1935-1940, 2016

      2 D. W. Jee, "Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform" 50 (50): 1263-1274, 2015

      3 G. Blasco, "Design of a stable pulse generator system based on a Ring-VCO Phase-Locked Loop using 180nm CMOS technology" 25-27, 2015

      4 B. Catli, "A sub-200fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications" 1-4, 2013

      5 H. Y. Chang, "A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65-nm CMOS technology" 62 (62): 543-555, 2014

      6 G. Jeon, "A low jitter PLL design using active loop fiter and low-dropout regulator for supply regulation" 223-224, 2015

      7 M. Ghasemzadeh, "A New Adaptive PLL to Reduce the Lock Time in 0. 18μm technology" 140-142, 2016

      8 J. Kim, "A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0. 13-μm CMOS" 41 (41): 899-908, 2006

      1 안성진, "전하펌프를 이용한 루프 필터 전압변화 보상 위상고정루프" 한국정보통신학회 20 (20): 1935-1940, 2016

      2 D. W. Jee, "Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform" 50 (50): 1263-1274, 2015

      3 G. Blasco, "Design of a stable pulse generator system based on a Ring-VCO Phase-Locked Loop using 180nm CMOS technology" 25-27, 2015

      4 B. Catli, "A sub-200fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications" 1-4, 2013

      5 H. Y. Chang, "A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65-nm CMOS technology" 62 (62): 543-555, 2014

      6 G. Jeon, "A low jitter PLL design using active loop fiter and low-dropout regulator for supply regulation" 223-224, 2015

      7 M. Ghasemzadeh, "A New Adaptive PLL to Reduce the Lock Time in 0. 18μm technology" 140-142, 2016

      8 J. Kim, "A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0. 13-μm CMOS" 41 (41): 899-908, 2006

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      공동연구자 (7)

      유사연구자 (20) 활용도상위20명

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2027 평가예정 재인증평가 신청대상 (재인증)
      2021-01-01 평가 등재학술지 유지 (재인증) KCI등재
      2018-01-01 평가 등재학술지 선정 (계속평가) KCI등재
      2017-12-01 평가 등재후보로 하락 (계속평가) KCI등재후보
      2013-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2011-11-23 학술지명변경 외국어명 : THE JOURNAL OF The KOREAN Institute Of Maritime information & Communication Science -> Journal of the Korea Institute Of Information and Communication Engineering KCI등재
      2011-11-16 학회명변경 영문명 : International Journal of Information and Communication Engineering(IJICE) -> The Korea Institute of Information and Communication Engineering KCI등재
      2011-11-14 학회명변경 한글명 : 한국해양정보통신학회 -> 한국정보통신학회
      영문명 : 미등록 -> International Journal of Information and Communication Engineering(IJICE)
      KCI등재
      2010-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2008-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2005-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2004-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2002-07-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.23 0.23 0.27
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.24 0.22 0.424 0.11
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