1 안성진, "전하펌프를 이용한 루프 필터 전압변화 보상 위상고정루프" 한국정보통신학회 20 (20): 1935-1940, 2016
2 D. W. Jee, "Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform" 50 (50): 1263-1274, 2015
3 G. Blasco, "Design of a stable pulse generator system based on a Ring-VCO Phase-Locked Loop using 180nm CMOS technology" 25-27, 2015
4 B. Catli, "A sub-200fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications" 1-4, 2013
5 H. Y. Chang, "A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65-nm CMOS technology" 62 (62): 543-555, 2014
6 G. Jeon, "A low jitter PLL design using active loop fiter and low-dropout regulator for supply regulation" 223-224, 2015
7 M. Ghasemzadeh, "A New Adaptive PLL to Reduce the Lock Time in 0. 18μm technology" 140-142, 2016
8 J. Kim, "A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0. 13-μm CMOS" 41 (41): 899-908, 2006
1 안성진, "전하펌프를 이용한 루프 필터 전압변화 보상 위상고정루프" 한국정보통신학회 20 (20): 1935-1940, 2016
2 D. W. Jee, "Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform" 50 (50): 1263-1274, 2015
3 G. Blasco, "Design of a stable pulse generator system based on a Ring-VCO Phase-Locked Loop using 180nm CMOS technology" 25-27, 2015
4 B. Catli, "A sub-200fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications" 1-4, 2013
5 H. Y. Chang, "A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65-nm CMOS technology" 62 (62): 543-555, 2014
6 G. Jeon, "A low jitter PLL design using active loop fiter and low-dropout regulator for supply regulation" 223-224, 2015
7 M. Ghasemzadeh, "A New Adaptive PLL to Reduce the Lock Time in 0. 18μm technology" 140-142, 2016
8 J. Kim, "A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0. 13-μm CMOS" 41 (41): 899-908, 2006