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あぁかがさざただなはばぱまやゃらわゎんいぃきぎしじちぢにひびぴみりうぅくぐすずつづっぬふぶぷむゆゅるえぇけげせぜてでねへべぺめれおぉこごそぞとどのほぼぽもよょろを

アァカサザタダナハバパマヤャラワヮンイィキギシジチヂニヒビピミリウゥクグスズツヅッヌフブプムユュルエェケゲセゼテデヘベペメレオォコゴソゾトドノホボポモヨョロヲ ―

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á à Á À é è É È ç Ç ê

Ä Ö Ü ä ö ü ß

ְ ֳ ֲ ֱ ָ ַ ֵ ֶ ִ ֹ ּ ֻ ׂ ׁ ּ פ ם ן ו ט א ר ק ף ך ל ח י ע כ ג ד ש ץ ת צ מ נ ה ב

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、。 · ‥ … ¨ 〃 ― ∥ ＼ ∼ ´ ～ ˇ ˘ ˝ ˚ ˙ ¸ ˛ ¡ ¿ ː ！＇，．／：；？＾＿｀｜

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Æ Ð Ħ Ĳ Ł Ø Œ Þ Ŧ Ŋ æ đ ð ħ ı ĳ ĸ ŀ ł ø œ ß þ ŧ ŋ ŉ

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RISS 인기검색어

LMS 적응 디지털 필터의 고속 처리를 위한 파이프라인 하드웨어 구조에 관한 연구 = A study on a pipelined hardware structure for high-speed processing of LMS adaptive digital filter

한글로보기

https://www.riss.kr/link?id=A106123043

저자

김진율 (수원대학교)
발행기관
水原大學校(THE UNIVERSITY OF SUWON )
학술지명
論文集(THESES COLLECTION)
권호사항

Vol.32 No.- [2018]
발행연도
2018
작성언어
Korean
주제어

LMS adaptive filter ; high-speed processing ; hardware structure
자료형태
학술저널
수록면

21-25(5쪽)
제공처
RISS
소장기관
- 수원대학교 중앙도서관
※ 대학의 dCollection(지식정보 디지털 유통체계)을 통하여 작성된 목록정보입니다.

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부가정보

다국어 초록 (Multilingual Abstract)

We present a methodology for designing a specialized hardware structure of the LMS adaptive filter with a
very high sampling rate and many taps, where real-time processing requirements can not be met with
conventional off-the-shelf DSP processors. We show that the excessive critical path delay of the conventional
LMS filter can be reduced and pipelined efficiently by introducing a bulk of delays in the input and the error
signals. And, to reduce the hardware requirements further, filter taps are divided into groups and hardware
resources are shared between groups by interleaving technique.

번역하기

We present a methodology for designing a specialized hardware structure of the LMS adaptive filter with a very high sampling rate and many taps, where real-time processing requirements can not be met with conventional off-the-shelf DSP processors. W...

We present a methodology for designing a specialized hardware structure of the LMS adaptive filter with a
very high sampling rate and many taps, where real-time processing requirements can not be met with
conventional off-the-shelf DSP processors. We show that the excessive critical path delay of the conventional
LMS filter can be reduced and pipelined efficiently by introducing a bulk of delays in the input and the error
signals. And, to reduce the hardware requirements further, filter taps are divided into groups and hardware
resources are shared between groups by interleaving technique.