Euro-DAC '93, European Design Automation Conference with Euro-VHDL '93 : proceedings, CCH Hamburg, Germany, September 20-24, 1993

목차 (Table of Contents)

• CONTENTS
• Welcome = ⅴ
• Steering Committee = ⅵ
• EURO-DAC '93 Program Committee = ⅷ
• EURO-VHDL '93 Committee = xi
• Architecture-Specific Synthesis／Chair : G. Saucier
• PEAS-I : A Hardware／Software Co-Design System for ASIPs / A. Alomary ; T. Nakata ; Y. Honma ; M. Imai ; J. Sato ; N. Hikichi = 2
• High-Level Synthesis Transformations for Programmable Architectures / P. P$$\ddot o$$chm$$\ddot u$$ller ; M. Glesner ; F. Longsen = 8
• GAUT : An Architectural Synthesis Tool for Dedicated Signal Processors / E. Martin ; O.Sentieys ; H. Dubois ; J. L. Philippe = 14
• Partitioning and Clustering／Chair : U. Lauther
• Post-Analysis-Based Clustering Dramatically Improves the Fiduccia-Mattheyses Algorithm / Y. Saab = 22
• A New Optimization Driven Clustering Algorithm for Large Circuits / C. L. Ding ; C. Y. Ho ; M. J. Irwin = 28
• A Performance Driven Hierarchical Partitioning Placement Algorithm / T. Gao ; C. L. Liu ; K. C. Chen = 33
• Partitioning Approach to Find an Exact Solution to the Fitting Problem in an Application-Specific EPLD Device / M. Chrzanowska-Jeske ; S. Goller = 39
• High-Level Synthesis／Chair : D. D. Gajski
• DSP Datapath Synthesis Eliminating Global Interconnect / A. A. Duncan ; D. C. Hendry = 46
• Regular Schedules for Scalabel Design of IIR Filters / H. Wang ; N. Dutt ; A. Nicolau = 52
• An Approach to Module Binding by Fuzzy Partitioning / R. Hermida ; M. Fern$$\acute a$$ndez ; F. Tirado ; P. Rup$$\acute e$$rez ; V. S$$\acute a$$nchez = 58
• Placement／Chair : F. Johannes
• A New Performance Driven Macro-Cell Placement Algorithm / T.S. Tia ; C.L. Liu = 66
• PCUBE : A Performance Driven Placement Algorithm for Low Power Designs / H. Vaishnav ; M. Pedram = 72
• Best-So-Far vs. Where-You-Are : New Perspectives on Simulated Annealing for CAD / K.D. Boese ; A.B. Kahng ; C.W.A. Tsao = 78
• Circuit and Multi-Level Simulation／Chair : J. Benkoski
• A Novel and Efficient Technique for Transient Analysis of Tightly Coupled Circuits : The Integral Equation Method(IEM) / M.N. Sabry ; M.S. Tawfik ; H. Eltahawy ; S. Garcia-Sabiro ; J. Besnard = 86
• A Consistent Nonlinear Simulation Environment Based on Improved Harmonic Balance Techniques / J.T. Yao ; A.T. Yang = 90
• Partitioning Strategies Within a Distributed Multilevel Logic Simulator Including Dynamic Repartitioning / N. Simic ; H. Ortner = 96
• Routing／Chair : J.P. Cohoon
• Graph Based Analysis of FPGA Routing / Y.-L. Wu ; M. Marek-Sadowska = 104
• On Over-the-Cell Channel Routing / T.-C. Wang ; D.F. Wong ; Y. Sun ; C.K. Wong = 110
• A New Global Routing Algorithm for Over-the-Cell Routing in Standard Cell Layouts / T. Koide ; S. Wakabayashi ; N. Yoshida = 116
• Formal Verification and Fault Tolerance／Chair : L. Claesen
• An Efficient Tool for System-Level Verification of Behaviors and Temporal Properties / P. Camurati ; F. Corno ; P. Prinetto = 124
• Dynamic Variable Reordering for BDD Minimization / E. Felt ; R. Brayton ; A. Sangiovanni-Vincentelli ; G. York = 130
• Computer-Aided Technique for Optimal Design of Defect-Tolerant VLSI with Built-In Redundancy / I. Shagurin ; A. Ivanov = 136
• "HW／SW Codesign : A New Trend in High-Level Design or Just a Slogan?"／Chair : A. Sauer PDAS : Processor Design Automation System / I. Pyo ; A.M. Despain = 144
• Heterogeneous System Level Specification and Design / Chair : J. Staunstrup
• Interface Specification and Synthesis for VHDL Processes / P. Gutberlet ; W. Rosenstiel = 152
• A Formal Model for Coupling Computer-Based Systems and Physical Systems / M. Brielmann ; B. Kleinjohann = 158
• State-Machine-Development-Tool for High-Level-Design Entry and Simulation / U. Br$$\ddot u$$ning ; G. Radke ; J. Sladky = 164
• Module Generation／Chair : M. Pedram
• Cell Area Minimization by Transistor Folding / T.W. Her ; D.F. Wong = 172
• Demosthenes - A Technology-Independent Power DMOS Layout Generator / G. Fourneris ; N. Bekkara ; J. Benkoski ; L. Zullino ; D. Spatafora ; G. Martino = 178
• JOGM : A CMOS Cell Layout Style Using Jogged Transistor Gates / R.D. Hindmarsh = 184
• Timing Analysis and Delay Faults／Chair : J. Benkoski
• GASTIM : A Timing Analyzer for GaAs Digital Circuits / A. Hern$$\acute a$$ndez ; L. G$$\acute o$$mez ; A. Nunez = 190
• Concurrent Path Sensitization in Timing Analysis / J.M. Silva ; K.A. Sakallah = 196
• Logic Systems for Path Delay Test Generation / S. Bose ; P. Agrawal ; V.D. Agrawal = 200
• Design for Testability／Chair : P. Prinetto
• Monitoring BIST by Covers / M. G$$\ddot o$$ssel ; H. J$$\ddot u$$rgensen = 208
• Layout-Level Design for Testability Rules for a CMOS Cell Library / M. Rull$$\acute a$$n ; J. Oliver ; C. Ferrer ; F.C. Blom = 214
• Test Function Embedding Algorithms with Application to Interconnected Finite State Machines / S. Kanjilal ; S.T. Chakradhar ; V.D. Agrawal = 219
• Scheduling and Allocation／Chair : M. Glesner
• Extended 0／1 LP Formulation for the Scheduling Problem in High-Level Synthesis / H. Achatz = 226
• Register Allocation for Data Flow Graphs with Conditional Branches and Loops / C. Park ; T. Kim ; C.L. Liu = 232
• Conditional and Unconditional Hardware Sharing in Pipeline Synthesis / U. Prabhu ; B.M. Pangrle = 238
• Architectural Tradeoffs in Synthesis of Pipelined Controls / L. Ramachandran ; D.D. Gajski = 244
• Test Pattern Generation and Diagnosis／Chair : F. Brglez
• A Method for Diagnosing Implementation Errors in Synchronous Sequential Circuits and its Implications on Synthesis / I. Pomeranz ; S.M. Reddy = 252
• REGGEN - Test Pattern Generation on Register Transfer Level / A. Magdolen ; J. Bezakova ; E. Gramatova ; M. Fischerova = 259
• On the Minimal Test Set for Single Fault Location / X. Sun ; F. Lombardi ; D. Sciuto = 265
• A Dynamic Communication Strategy for the Distributed ATPG System DPLATION / M.J. Aguado ; C. L$$\acute o$$pez-Barrio ; M.A. Miranda ; E. de la Torre = 271
• Specific Areas of Concurrent Engineering／Chair : K.H. Diener
• The CALLAS Synthesis System and its Application to Mechatronic ASIC Design Problems / P. Windirsch ; P. Duzy = 278
• A Practical Approach to EMC for Printed Circuit Board (PCB) and Multichip Module (MCM) Design / J. Berrie ; A. Slade = 284
• CAD : The Numerical and Analytical Methods Combined for the Analysis of IC's Thermal Fields / V.A. Koval ; I.V. Farmaga ; D.V. Fedasyuk ; A.I. Ostapchuk = 290
• SPAN : Tightly Coupled Thermal and Electrical Simulation / B. Klaassen ; K.L. Paap = 294
• FPGA Synthesis／Chair : K.C. Chen
• GAFPGA : Genetic Algorithm for FPGA Technology Mapping / V. Kommu ; I. Pomeranz = 300
• Realizing Expression Graphs Using Table-Lookup FPGAs / I. Levin ; R.Y. Pinter = 306
• A New Logic Minimization Method for Multiplexor-Based FPGA Synthesis / R.P. Jacobi ; A.M. Trullemans = 312
• Technology Mapping for Sequential Circuits Based on Retiming Techniques / U. Weinmann ; W. Rosenstiel = 318
• Framework Components／Chair : O. Olesen
• An Approach to CAD Database Support of Design Consistency Control / B. Despr$$\acute e$$s ; R. Piloty ; U. Schellin = 326
• Concepts and Methods for Version Modeling / C. Oussalah ; G. Talens ; M.F. Colinas = 332
• The MODES Global Control Environment. A Tool for Rapid Prototyping / C. Munk ; P. Ukelo ; A. Vachoux ; D. Mlynek = 338
• Boolean Matching and Spectral Methods／Chair : W. Rosenstiel
• Boolean Matching Based on Boolean Unification / K.C. Chen = 346
• Fast Boolean Matching for Field-Programmable Gate Arrays / K. Zhu ; D.F. Wong = 352
• An Iterative Combinational Logic Synthesis Technique Using Splectral Information / M.A. Thornton ; V.S.S. Nair = 358
• Framework Implementations／Chair : J. Heaton
• Implementation of the Conception of Flexible Integration Within the CADS Framework / V.A. Shepelev ; A.V. Vlasov = 366
• Aspects of Realizing the CFI Design Representation Specification in the Nelsis Framework / P. Kist ; R. van Leuken ; M. Sim = 372
• BEPPO : A Data Model for Design Representation / O. Schettler ; A. Bredenfeld = 378
• Design Topics in Logic Synthesis／Chair : G. Musgrave
• Retiming by Combination of Relocation and Clock Delay Adjustment / H.G. Martin = 384
• Multi-Way FSM Decomposition Based on Interconnect Complexity / W.L. Yang ; R.M. Owens ; M.J. Irwin = 390
• State Assignment for Finite State Machines Using T Flip-Flops / G. Rietsche = 396
• On the Implementation of an Efficient Performance Driven Generator for Conditional-Sum-Adders / B. Becker ; R. Drechsler ; P. Molitor = 402
• User View of Testing and Timing／Chair : J. Hillawi
• An HDL Approach to Board-Level BIST / G.R. Alves ; M.G. Gericota ; J.L. Ramalho ; J.M.M. Ferreira = 410
• Technology Independent Boundary Scan Synthesis (Design Flow Issues) / M.F. Robinson = 416
• Next Generation Environment for Extremely Fast Test Pattern Generation / G. Pulini ; S. Hamacher = 422
• TONIC : A Timing Database for VLSI Design / S. Rusu ; G. Schulte ; S. Taylor ; P. Tong = 426
• VHDL and Testing／Chair : J. Mermet
• Hierarchical Test Generation : Where We Are, and Where We Should Be Going / J.R. Armstrong = 434
• On the Modeling and Testing of VHDL Behavioral Description of Sequential Circuits / V. Pla ; J.F. Santucci ; N. Giambiasi = 440
• Test Generation Based on Synthesizable VHDL Descriptions / M. Karunaratne ; M. Masud = 446
• Modeling with VHDL／Chair : W. Nebel
• Top-Down Modeling of RISC Processors in VHDL / H.P. Juan ; N.D. Holmes ; S. Bakshi ; D.D. Gajski = 454
• Modeling of Real Bistables in VHDL / A.J. Acosta ; A. Barriga ; M. Valencia ; M.J. Bellido ; J.L. Huertas = 460
• A Workbench for Generation of Component Models / M. Bl$$\ddot u$$ml ; M. Lenzen ; A. Pawlak = 466
• Design Techniques in VHDL／Chair : J. Hillawi
• Analysis of Multi-Process VHDL Specifications with a Petri Net Model / J. M$$\ddot u$$ller ; H. Kr$$\ddot a$$mer = 474
• The Concept of Superprocesses for High-Level Synthesis and Their VHDL Modelling / P. Keresztes ; I. Agotai = 480
• Synchronous Designs in VHDL / A. Debreil ; P. Oddo = 486
• System-Level-Specification and Design／Chair : F. Rammig
• High-Level Modeling Using Extended Timing Diagrams / P. Moeschler ; H.P. Amann ; F. Pellandini = 494
• Using VHDL for HW／SW Co-Specification / W. Ecker = 500
• Industrial Experimentation of High-Level Synthesis / P. Kission ; A.A. Jerraya ; L. Bergher ; E. Closse = 506
• Formal Methods／Chair : D. Borrione
• A Net-Based Semantics for VHDL / W. Damm ; B. Josko ; R. Schl$$\ddot o$$r = 514
• A Framework for Macro-and Micro-Time to Model VHDL Attributes / M. Belhadj ; R. McConnell ; P. Le Guernic = 520
• Toward a Formal Semantics of IEEE Std. VHDL 1076 / S. Olcoz ; J.M. Colom = 526
• Specification and Simulation／Chair : E. Villar
• Modelling Aspects of System Level Design / F.J. Rammig = 534
• Features Supporting System-Level Specification in HDLs / S. Narayan ; D.D. Gajski = 540
• VHD$$_e$$LDO : A New Mixed Mode Simulation / H. El Tahawy ; D. Rodriguez ; S. Garcia-Sabiro ; J.-J. Mayol = 546
• VHDL and Synthesis／Chair : S. M$$\ddot a$$rz
• Functional-Level Synthesis with VHDL / J.P. Calvez ; D. Heller ; P. Bakowski = 554
• Synthesis of Functions and Procedures in Behavioral VHDL / L. Ramachandran ; S. Narayan ; F. Vahid ; D.D. Gajski = 560
• Synthesis of Complex VHDL Operators / M. Gasteier ; M. Glesner ; N. Wehn = 566
• Locally Optimistic Methods of Concurrent Simulation / D.K. Arvind = 572
• Author Index = 577