칩 멀티 프로세서 구조에서 온칩 유휴 캐시의 효과적인 활용 방안

다국어 초록 (Multilingual Abstract)

Recently, although the number of cores on a chip multi-processor increases, multi-programming or multi-threaded programming techniques to utilize the whole cores are still insufficient. Therefore, there inevitably exist some idle cores which are not working. This results in a waste of the caches, so-called idle caches which are dedicated to those idle cores. In this research, we propose amethodology to exploit idle caches effectively as victimcaches of on-chip memory resource. In simulation results, we have achieved 19.4%and 10.2%IPC improvement in 4-core and 16-core respectively, compared to previous technique.

참고문헌 (Reference)

1 M., Zhang, "Victim replication: Maximizing capacity while hiding wire delay in tiled CMPs" 336-345, 2005

2 S. Borkar, "Thousand Core Chips-A Technology Perspective" 746-749, 2007

3 Intel Corporation, "TeraFlops Research Chip" 2007

4 Z. Chishti, "Optimizing replication, communication and capacity allocation in CMPs" 357 (357): 357-368, 2005

5 D. Choffines, "Migration policies for multi-core fair-share scheduling" 42 (42): 2008

6 N., Jouppi, "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers" 364-373, 1990

7 W. Qin, "Flexible and FormalModeling of Microprocessors with Application to Retargetable Simulation" 10556-, 2003

8 Jichuan, Chang, "Cooperative Caching for Chip Multiprocessors" 264-276, 2006

9 C. Kim, "An adaptive, non-uniformcache structure for wire-delay dominated on-chip caches" X : 211-222, 2002

10 H. Dybdahl, "An Adaptive Shared/Private NUCA Cache Partitioning Scheme for ChipMultiprocessors" 2-12, 2007

11 B. M. Beckmann, "ASR: Adaptive Selective Replication for CMP Caches" 443-454, 2006

12 J. Huh, "A NUCA Substrate for Flexible CMP Cache Sharing" 18 (18): 1028-1040, 2007