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      New Thyristor Based ESD Protection Devices with High Holding Voltages for On-Chip ESD Protection Circuits

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      https://www.riss.kr/link?id=A106172891

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      다국어 초록 (Multilingual Abstract)

      In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness
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      In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recogniz...

      In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness

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      참고문헌 (Reference)

      1 Chris Toumazou, "Trade-Offs in analog Circuit Design" Kluwer Academic Publishers 139-2004,

      2 A. Djemouai, "New CMOS Integrated Pulse Width Modulator for Voltage Conversion Applications" 2000

      3 R. G Wagner, "Extend and Cost of EOS / ESD Damage in an IC Manufacturing Process "" 49-55, 1993

      4 A. Amerasekera, "ESD in silicon integrated circuits" Wiley 2005

      5 Lu Chen, "Design and Test of a Synchronous PWM Switching Regulator System" 2000

      6 Baker, "CMOS Circuit Design and layout" Wiley 900-,

      7 K. Mark Smith, Jr, "A Comparison of Voltage-Mode Soft-Switching Methods for PWM Converters" 12 (12): 1997

      1 Chris Toumazou, "Trade-Offs in analog Circuit Design" Kluwer Academic Publishers 139-2004,

      2 A. Djemouai, "New CMOS Integrated Pulse Width Modulator for Voltage Conversion Applications" 2000

      3 R. G Wagner, "Extend and Cost of EOS / ESD Damage in an IC Manufacturing Process "" 49-55, 1993

      4 A. Amerasekera, "ESD in silicon integrated circuits" Wiley 2005

      5 Lu Chen, "Design and Test of a Synchronous PWM Switching Regulator System" 2000

      6 Baker, "CMOS Circuit Design and layout" Wiley 900-,

      7 K. Mark Smith, Jr, "A Comparison of Voltage-Mode Soft-Switching Methods for PWM Converters" 12 (12): 1997

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2026 평가예정 재인증평가 신청대상 (재인증)
      2020-01-01 평가 등재학술지 유지 (재인증) KCI등재
      2017-01-01 평가 등재학술지 선정 (계속평가) KCI등재
      2016-01-01 평가 등재후보학술지 유지 (계속평가) KCI등재후보
      2014-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.32 0.32 0
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0 0 0 0.1
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