Introduction to switching theory and logical design

목차 (Table of Contents)

• CONTENTS
• 1 / Introduction = 1
• 1.1 Characteristics of Digital Systems = 1
• 1.2 A Brief Historical Note = 4
• 1.3 Organization of Digital Computers = 5
• 1.4 Types of Digital Circuits = 7
• 2 / Number Systems = 9
• 2.1 Introduction = 9
• 2.2 Conversion between Bases = 10
• 2.3 Arithmetic with Bases Other than I en = 44
• 2.4 Negative Numbers)6
• 2.5 Binary-Coded Decimal Numbers = 18
• Problems = 19
• Bibliography = 21
• 3 / Truth Functions = 23
• 3.1 Introduction = 23
• 3.2 Binary Connectives = 26
• 3.3 Evaluation of Truth Functions = 28
• 3.4 Many-Statement Compounds = 29
• 3.5 Physical Realizations = 30
• 3.6 Sufficient Sets of the Connectives = 35
• 3.7 A Digital Computer Example = 38
• Problems = 41
• Bibliography = 43
• 4 / Boolean Algebra = 45
• 4.1 Introduction = 45
• 4.2 Truth-Functional Calculus as a Boolean Algebra = 47
• 4.3 Duality = 48
• 4.4 Fundamental Theorems of Boolean Algebra = 49
• 4.5 Set Theory as an Example of Boolean Algebra = 53
• 4.6 Examples of Boolean Simplification = 56
• 4.7 Remarks on Switching Functions = 61
• 4.8 Summary = 64
• Problems = 65
• Bibliography = 67
• 5 Switching Devices = 69
• 5.1 Introduction = 69
• 5.2 Switches and Relays = 69
• 5.3 Logic Circuits = 71
• 5.4 Speed and Delay in Logic Circuits = 77
• 5.5 Integrated Circuit Logic = 79
• 5.6 Comparison of IC Logic Families = 86
• 5.7 Logical Interconnection of NAND and NOR Gates = 88
• 5.8 Conclusion = 95
• Bibliography = 96
• 6 / Minimization of Boolean Functions = 97
• 6.1 Introduction = 97
• 6.2 Standard Forms of Boolean Functions = 98
• 6.3 Minterm and Maxterm Designation of Functions = 101
• 6.4 Karnaugh Map Representation of Boolean Functions = 103
• 6.5 Simplification of Functions on Karnaugh Maps = 114
• 6.6 Map Minimizations of Product-of-Sums Expressions = 126
• 6.7 Incompletely Specified Functions = 129
• Problems = 133
• Bibliography = 137
• 7 / Tabular Minimization and Multiple-Output Circuits = 139
• 7.1 Cubical Representation of Boolean Functions = 139
• 7.2 Determination of Prime Implicants = 142
• 7.3 Selection of an Optimum Set of Prime Implicants = 148
• 7.4 Multiple-Output Circuits = 159
• 7.5 Map Minimization of Multiple-Output Circuits = 161
• 7.6 Tabular Determination of Multiple-Output Prime Implicants = 166
• Problems = 168
• Bibliography = 174
• 8 / Special Realizations and Codes = 175
• 8.1 Introduction = 175
• 8.2 The Binary Adder = 176
• 8.3 Coding of Numbers = 181
• 8.4 The Decoder = 185
• 8.5 Code Conversion and Read-Only Memories = 188
• 8.6 NAND and NOR Implementation = 194
• 8.7 Parity = 199
• 8.8 Error-Detecting-and-Correcting Codes = 202
• 8.9 Hamming Codes = 204
• Problems = 1
• Bibliography = 210
• 9 / Introduction to Sequential Circuits = 211
• 9.1 General Characteristics = 211
• 9.2 Flip-Flops = 213
• 9,3 Why Sequential Circuits? = 217
• 9.4 Shift Registers and Counters = 221
• 9.5 Speed-Versus-Cost Trade-Off = 223
• 9.6 A General Model for Sequential Circuits = 226
• 9.7 Clock Mode and Pulse Mode Sequential Circuits = 227
• 9.8 Timing Problems and Master-Slave Flip-Flops = 230
• 9.9 Level Mode Sequential Circuits = 235
• 9.10 Conclusion = 236
• Problems = 237
• Bibliography = 239
• 10 / Synthesis of Clock Mode Sequential circuits = 241
• 10.1 Analysis of a Sequential Circuit = 241
• 10.2 Design Procedure = 244
• 10.3 Synthesis of State Diagrams = 245
• 10.4 Finite Memory Circuits = 249
• 10.5 Equivalence Relations = 256
• 10.6 Equivalent States and Circuits = 258
• 10.7 Determination of Classes of Indistinguishable States = 261
• 10.8 Simplification by Implication Tables = 267
• 10.9 State Assignment and Memory Element Input Equations = 275
• 10.10 Partitioning and State Assignment = 289
• 10.11 Conclusion = 299
• Problems = 300
• Bibliography = 305
• 11 / Pulse-Mode Circuits = 307
• 11.1 Introduction = 307
• 11.2 Mealy Circuits and Moore Circuits = 309
• 11.3 Design Procedures = 311
• 11.4 Mealy Moore Translations = 317
• 11.5 Counters Revisited = 323
• Problems = 326
• Bibliography = 328
• 12 / Incompletely Specified Sequential Circuits = 329
• 12.1 Introduction = 329
• 12.2 Compatibility = 332
• 12.3 Completion of Design = 350
• Problems = 355
• Bibliography = 361
• 13 / Level Mode Sequential Circuits = 363
• 13.1 Introduction = 363
• 13.2 Analysis of a Fundamental Mode-ircuit = 366
• 13.3 Synthesis of Flow Tables = 367
• 13.4 Minimization = 370
• 13.5 Transition Tables, Excitation Maps, and Output Maps = 376
• 13.6 Cycles and Races = 379
• 13.7 Race-Free Assignments = 382
• 13.8 Hazards ; it Sequential Circuits = 394
• 13.9 General Level Mode Circuits = 401
• Problems = 409
• Bibliography = 417
• 14 / A Second Look at Flip-flops and Timing = 419
• 14.1 Introduction = 419
• 14.2 Clock Skew = 420
• 14.3 A Flow Table for a J-K Master-Slave Flip-Flop = 421
• 14.4 Another Approach to Level Mode Realization = 424
• 14.5 Realizing the Standard J-K Flip-Flop = 426
• 14.6 Analysis of Races and Hazards = 429
• 14.7 Summary = 435
• Problems = 435
• Bibliography = 436
• 15 / Description of Large Sequential Circuits = 437
• 15.1 Introduction = 437
• 15.2 Clock Input Control = 438
• 15.3 Extended State Table = 440
• 15.4 A-Program Description = 442
• 15.5 Synthesis = 443
• 15.6 Vector operations = 454
• 15.7 Logical Functions of Vectors = 456
• 15.8 Applications = 460
• 15.9 Summary = 468
• Problems = 468
• Bibliography = 472
• 16 / LSI-MSI = 473
• 16.1 Introduction = 473
• 16.2 Definitions = 474
• 16.3 Design with Standard MSI Parts = 476
• 16.4 Basic Economics of Integrated Circuits = 484
• 16.5 MOS / LSI = 489
• 16.6 Simulation = 495
• 16.7 Test Sequence Generation = 500
• Problems = 502
• Bibliography = 504
• 17 / Combinational Functions with Special Properties = 507
• 17.1 Introduction = 507
• 17.2 Symmetric Functions = 508
• 17.3 Boolean Combinations of Symmetric Functions = 510
• 17.4 Higher-Order Forms = 512
• 17.5 Simple Disjoint Decomposition = 515
• 17.6 Complex Disjoint Decomposition = 523
• 17.7 Iterative Networks = 529
• 17.8 Ordering Relations = 534
• 17.9 Unate Functions = 536
• Problems = 540
• Bibliography = 542
• 18 / Threshold Logic = 545
• 18.1 Generalized Resistor-Transitor Logic Circuit = 545
• 18.2 Linear Separability = 548
• 18.3 Conditions for Linear Separability = 553
• 18.4 Magnetic Threshold Logic Devices = 560
• 18.5 The Realization of Symmetric Functions Using More than One Threshold Device = 562
• Problems = 568
• Bibliography = 570
• Appendix A / Selection of Minimal Closed Covers Bibliography = 571
• Bibliography = 579
• Appendix B / Relay Circuits = 580
• B.1 Basic Characteristics of Relay Circuits = 580
• B.2 Relay Realizations of Symmetric Functions = 585
• B.3 Relays in Sequential Circuits = 586
• Bibliography = 592