Energy-efficient sensor interface and high-speed memory circuits for IoT systems

국문 초록 (Abstract)

본 논문은 에너지 제약이 큰 사물인터넷(IoT) 센서 노드가 제한된 전력·폼팩터 예산 내에서 센싱, 처리, 저장, 통신을 수행해야 한다는 요구를 다룬다. 이를 위해 시간 영역(time‑domain) 기반 센서 인터페이스와 공정·전압·온도(PVT) 변화에 강인한 임베디드 STT‑MRAM 읽기 인터페이스를 개발하여 에너지 효율과 신뢰성을 동시에 향상시킨다.
이식형 안구내압 (IOP) 모니터링을 위해 RC 지연 기반 Half‑Wheatstone‑bridge‑to‑digital converter (HBDC)를 제안한다. HBDC는 두 Half‑Wheatstone-bridge (H-WhB)의 RC 충전 지연이 일치하도록 커패시터 DAC(CDAC)을 조정하고, 그때의 CDAC 코드로 저항비를 양자화한다. 또한 잡음에 민감한 비트 위치만 선택적으로 반복 평가한 뒤 다수결로 결정하는 비트‑레벨 오버샘플링(BOS)을 도입하였다. 180‑nm CMOS 구현에서 11.52 ms 변환 시간에 12.79 µW 전력으로 0.24 mmHg(1σ) 해상도와 8.58 nJ·mmHg² FoM을 달성하였다.
시간 영역 개념은 CMOS 실리콘 응력 센싱으로 확장된다. 듀얼‑폴라리티 로제트와 MOSFET 센싱 소자를 사용하고, 큰 응력에 의해 전류 불균형이 커져도 내부 노드가 붕괴되지 않도록 소싱 전류 보조(current‑assisted) 커런트 미러 프론트엔드를 적용하였다. 후단은 차동 전류‑제어 발진기(CCO)와 듀얼‑엣지 카운터 기반의 전류/시간 영역 리드아웃으로 구성되어, 변환 시간으로 해상도–에너지 트레이드오프를 디지털로 설정한다. 180‑nm CMOS 칩은 1.5 V에서 225.6 nW를 소모하며 0–375 MPa 범위에서 0.27 MPa(1σ) 해상도(0.05 nJ·MPa² FoM)를 달성한다.
임베디드 비휘발성 저장을 위해 28‑nm FD‑SOI 공정의 16 Mb STT‑MRAM 매크로에 배열 적응형 이중 기준(AADR)과 이중 기준 센스 앰프(DRSA)를 결합하였다. AADR은 배열별로 P/AP 기준을 분포 꼬리(tail)에 맞게 디지털로 조정하고, DRSA는 두 기준을 동시에 사용해 읽기 마진을 확장한다. BER ≤ 10⁻⁶ 조건에서 요구 읽기 액세스 시간은 −40 °C/25 °C에서 18–35%, 125 °C에서 30% 단축되며, zero‑BER 읽기 윈도우는 온도 전 범위에서 최대 약 3배 확대된다. 또한 0.9 V, 25 °C에서 2.0 ns 읽기와 0.6 pJ/bit 읽기 에너지(125 °C에서 3.3 ns)를 달성한다.

다국어 초록 (Multilingual Abstract)

This dissertation addresses energy‑constrained Internet‑of‑Things (IoT) nodes that must sense, process, store, and communicate data within tight power and form‑factor budgets. It develops time‑domain sensor interfaces and a PVT‑tolerant embedded STT‑MRAM read interface to improve energy efficiency and robustness.
For implantable intraocular pressure (IOP) monitoring, an RC‑delay‑based half‑Wheatstone‑bridge‑to‑digital converter (HBDC) quantizes resistance by tuning a capacitor DAC (CDAC) until RC‑charging delays of two half‑bridge branches match. An energy‑efficient bit‑level oversampling (BOS) selectively repeats only noise‑sensitive bit decisions with majority voting. In 180‑nm CMOS, the HBDC achieves 0.24 mmHg (1σ) resolution at 12.79 µW with 11.52 ms conversion time (8.58 nJ·mmHg² FoM).
The time‑domain approach is extended to CMOS silicon stress sensing using a dual‑polarity rosette and MOSFET sensing elements. A sourcing‑current‑assisted current‑mirror front‑end prevents internal node collapse under large stress‑induced imbalance, and a current/time‑domain readout based on differential current‑controlled oscillators (CCOs) and dual‑edge counters sets the resolution–energy trade‑off via conversion time. Implemented in 180‑nm CMOS, the prototype consumes 225.6 nW (1.5 V) and achieves 0.27 MPa (1σ) resolution over 0–375 MPa (0.05 nJ·MPa² FoM).
For embedded non‑volatile storage, a 16 Mb STT‑MRAM macro in 28‑nm FD‑SOI combines array‑adaptive dual references (AADR) with a dual‑reference sense amplifier (DRSA). AADR digitally tunes per‑array P/AP references to the local distribution tails, and DRSA senses against both to enlarge read margin. For BER ≤ 10⁻⁶, the required read access time is reduced by 18–35% at −40 °C/25 °C and by 30% at 125 °C, while the zero‑BER read window widens by up to ~3×. The macro achieves 2.0 ns read access and 0.6 pJ/bit read energy at 0.9 V and 25 °C (3.3 ns at 125 °C).
Overall, the proposed time‑domain sensing and dual‑reference STT‑MRAM circuits provide practical foundations for ultra‑low‑energy IoT systems.

목차 (Table of Contents)

• Chapter 1. Introduction 1
• 1.1. Introduction of Sensor Interface and Memory Interface for IoT System 1
• 1.2. Dissertation Contribution 4
• 1.3. Dissertation Organization 8
• Chapter 2. An RC Delay-Based Pressure-Sensing System with Energy-Efficient Bit-Level Oversampling Techniques for Implantable IOP Monitoring Systems 11
• 2.1. Introduction 11
• 2.2. Principle of RC Delay Readout Circuits 16
• 2.3. Principle of Optimal RC Charging Time (tmax) 17
• 2.4. Overall Architecture and Block Implementation Detail 20
• A. Overall architectures 20
• B. Half-Wheatstone-bridge-to-digital converter conversion process 20
• C. Capacitor bank 25
• D. Auto-zeroing amplifier and dynamic comparator 27
• E. Constant parasitic capacitance switch 30
• F. Offset, Mismatch, and Calibration Considerations 32
• 2.5. Energy-Efficient Bit-Level-Oversampling 34
• A. Conventional Oversampling 35
• B. Principle of Bit-Level Oversampling 36
• C. Bit-Level Oversampling Strategy 40
• 2.6 Noise Analysis 45
• A. System-Level Noise Model 45
• B. Conversion from Pressure to Resistance Domain 45
• C. Quantization Noise and Resistance-Domain Noise Decomposition 46
• D. Sensor Thermal Noise vs. Front-End Noise 47
• E. Effect of BOS on Minimum Detectable Resistance Resolution 48
• F. Summary and Design Implications 50
• 2.7 Measurement Results 51
• A. RC charging margin time for tmax 53
• B. Linearity 54
• C. Resolution and FoM 54
• D. System inaccuracy 56
• E. Supply voltage sensitivity 56
• F. Temperature sensitivity 57
• G. Power breakdown 58
• 2.8. Comparison with prior state-of-the-art 60
• 2.9. Conclusion 61
• Chapter 3. A 225.6 nW Energy-Efficient Time-domain CMOS Silicon Stress Sensor Interface 63
• 3.1. Introduction 63
• 3.2. Resistive Sensor Rosettes on (100) Silicon: Theoretical Foundations 68
• 3.3. Theory of MOSFET Devices on (100) Silicon 75
• 3.4. Design of Stress Elements 78
• 3.5. Design and Implementation of Stress Sensing Circuits 82
• A. Overall architectures 82
• B. Current-mirror based sensor-front-end interface 83
• C. Current-controlled oscillator (CCO) 86
• D. Ultra-low-power amplifier 87
• E. Stress tolerance layout techniques for peripheral circuits 88
• F. Offset, Mismatch, and Calibration Considerations 89
• 3.6 Measurement Results 93
• A. Measurement Setup 93
• B. Standalone MOSFET 95
• C. Linearity 97
• D. Resolution 98
• E. System inaccuracy 99
• F. Supply voltage sensitivity 102
• G. Temperature Sensitivity 102
• H. Repeated bending measurement for stability 103
• I. Power breakdown 104
• 3.7 Comparison with prior state-of-the-art 106
• 3.8 Conclusion 107
• Chapter 4. A 16 Mb 28 nm FD-SOI STT-MRAM Using PVT-Variation-Tolerant Dual-Reference Sensing Scheme 109
• 4.1. Introduction 109
• 4.2. Basics of STT-MRAM Operation 112
• 4.3. Dual-Reference Sensing Scheme 115
• 4.4. Measurement Results 123
• A. Measurement Setup 124
• B. Read Bit-Error Rate (BER) vs. read access time 125
• C. Read window 127
• D. Read Shmoo plot 130
• 4.5 Comparison with prior state-of-the-art 133
• 4.6 Conclusion 134
• Chapter 5. Conclusion 137
• 5.1 Summary of Contributions 137
• 5.2 Future Research Directions 139
• References 142
• Korean Abstract 158