포토리소그래피와 식각 공정 편차를 고려한 CNTFET SRAM 성능 분석에 관한 연구 = A study on the Performance Analysis of CNTFET SRAM considering Photolithography and Etching Process Variation

다국어 초록 (Multilingual Abstract)

As scaling to improve the performance of conventional silicon-based transistor approaches physical limits, global semiconductor companies and research institutes, including TSMC, are showing interest in CNTFETs that place CNTs, which can control current at a higher density than existing silicon-based current channels, between the source and drain of the transistor. However, because of the immaturity of the CNTFET manufacturing process, it is difficult to configure a circuit using only CNTFETs, so various studies have actively been conducted to use traditional MOSFETs and CNTFETs together in a circuit. In this paper, we discuss the analysis of SRAM performance changes due to photolithography and etching process deviations. The experimental results show that the CNTFET SRAM and hybrid SRAM show about 1.1 times and 2.6 times increase in standard deviation compared to the conventional MOSFET SRAM during write operation, but about 488 times and 2 times decrease in standard deviation during read operation. Based on these results, it can be found that the performance variation due to photolithography and etching process deviation can be generally reduced when CNTFETs are included in SRAM.