1 S. Bhattacharya, "Transformations and Resynthesis for Testability of RTL Control-Data Path Specifications" 1 : 304-318,
2 R. S. Fetherson, "Testability Features of AMD-K6TM Microprocessor" 64-69, 1998.
3 D. Bhavsar, "Testability Access of the High Speed Test Features in the Alpha 21264 Microprocessor" 487-495, 1998.
4 B. Norwood, "Orthogonal SCAN:Low Overhead SCAN for Data Paths" 659-668, 1996.
5 V. Fernandez, "High-level test synthesis based on controller redefinition" 1596-1597, 1997.
6 Mike Tien, "High-Level Test Syntheis of Dighital VLSI Circuits" Artech House 1997.
7 S. Bhattacharya, "H_SCAN:A High Level Alternative to Full-Scan Testing with Reduced Area and Test Application Overheads" 74-80, 1996.
8 I. Ghosh, "Design for Hierarchical Testability of RTL Circuits Obtained by Behavioral Synthesis" 173-179, 1995.
9 I. Ghosh, "A Design-for-Testability Technique for Register-Transfer Level Circuits Using Control/Data Flow Extraction" 706-723, 1998.
10 S. Ohtake,, "A DFT Method for RTL Circuits to Achieve Complete Fault Efficiency Based on Fixed-control Testability" 331-334, 2001.
1 S. Bhattacharya, "Transformations and Resynthesis for Testability of RTL Control-Data Path Specifications" 1 : 304-318,
2 R. S. Fetherson, "Testability Features of AMD-K6TM Microprocessor" 64-69, 1998.
3 D. Bhavsar, "Testability Access of the High Speed Test Features in the Alpha 21264 Microprocessor" 487-495, 1998.
4 B. Norwood, "Orthogonal SCAN:Low Overhead SCAN for Data Paths" 659-668, 1996.
5 V. Fernandez, "High-level test synthesis based on controller redefinition" 1596-1597, 1997.
6 Mike Tien, "High-Level Test Syntheis of Dighital VLSI Circuits" Artech House 1997.
7 S. Bhattacharya, "H_SCAN:A High Level Alternative to Full-Scan Testing with Reduced Area and Test Application Overheads" 74-80, 1996.
8 I. Ghosh, "Design for Hierarchical Testability of RTL Circuits Obtained by Behavioral Synthesis" 173-179, 1995.
9 I. Ghosh, "A Design-for-Testability Technique for Register-Transfer Level Circuits Using Control/Data Flow Extraction" 706-723, 1998.
10 S. Ohtake,, "A DFT Method for RTL Circuits to Achieve Complete Fault Efficiency Based on Fixed-control Testability" 331-334, 2001.
11 S. Dey, "A Controller-Based Design-for-Testability Technique for Controller-Data Path Circuits" 534-540, 1995.
12 I. Ghosh, "A BIST Scheme for RTL Circuits Based on Symbolic Testability Analysis" 19 (19): 111-128, Jan.2000